Issued Patents All Time
Showing 25 most recent of 97 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12368137 | High bandwidth die to die interconnect with package area reduction | Chonghua Zhong, Kunzhong Hu | 2025-07-22 |
| 12322730 | Wafer reconstitution and die-stitching | Sanjay Dabral, Kwan-Yu Lai, Kunzhong Hu, Vidhya Ramachandran | 2025-06-03 |
| 12283549 | High density interconnection using fanout interposer chiplet | Chonghua Zhong, Kunzhong Hu | 2025-04-22 |
| 12261132 | Structure and method for sealing a silicon IC | Vidhya Ramachandran, Sanjay Dabral, SivaChandra Jangam, Kunzhong Hu | 2025-03-25 |
| 12249599 | Multiple chip module trenched lid and low coefficient of thermal expansion stiffener ring | Wei Chen, Jie Zhao, Po-Hao Chang, Hsien-Che Lin, Ying-Chieh Ke +1 more | 2025-03-11 |
| 12159835 | High density 3D interconnect configuration | Sanjay Dabral, Zhitao Cao, Kunzhong Hu | 2024-12-03 |
| 12134870 | Fluctuation zone state slope protection system that responds to hydrological changes | Rong Li | 2024-11-05 |
| 12119275 | Recessed lid and ring designs and lid local peripheral reinforcement designs | Wei Chen, Jie Zhao | 2024-10-15 |
| 12087689 | Selectable monolithic or external scalable die-to-die interconnection system methodology | Sanjay Dabral, Jung-Cheng Yeh, Kunzhong Hu, Raymundo M. Camenforte, Thomas Hoffmann | 2024-09-10 |
| 12074077 | Flexible package architecture concept in fanout | Karthik Shanmugam, Flynn Carson, Raymundo M. Camenforte, Menglu Li | 2024-08-27 |
| 12068324 | Multi-die fine grain integrated voltage regulation | Jared L. Zerbe, Emerson S. Fang, Shawn Searles | 2024-08-20 |
| 12033982 | Fully interconnected heterogeneous multi-layer reconstructed silicon device | — | 2024-07-09 |
| 12021035 | Interconnecting dies by stitch routing | Sanjay Dabral | 2024-06-25 |
| 11967528 | Structure and method for fabricating a computing system with an integrated voltage regulator module | Vidhya Ramachandran, Chonghua Zhong, Kunzhong Hu, Shawn Searles, Joseph T. DiBene, II +1 more | 2024-04-23 |
| 11908819 | Semiconductor packaging substrate fine pitch metal bump and reinforcement structures | Jun Chung Hsu, Chih-Ming Chung, Yifan Kao, Young Doo Jeon, Taegui Kim | 2024-02-20 |
| 11862557 | Selectable monolithic or external scalable die-to-die interconnection system methodology | Sanjay Dabral, Jung-Cheng Yeh, Kunzhong Hu, Raymundo M. Camenforte, Thomas Hoffmann | 2024-01-02 |
| 11824015 | Structure and method for sealing a silicon IC | Vidhya Ramachandran, Sanjay Dabral, SivaChandra Jangam, Kunzhong Hu | 2023-11-21 |
| 11749631 | Electronic package including a hybrid thermal interface material and low temperature solder patterns to improve package warpage and reliability | Wei Chen, Kunzhong Hu | 2023-09-05 |
| 11735526 | High density 3D interconnect configuration | Sanjay Dabral, Zhitao Cao, Kunzhong Hu | 2023-08-22 |
| 11735567 | Wafer reconstitution and die-stitching | Sanjay Dabral, Kwan-Yu Lai, Kunzhong Hu, Vidhya Ramachandran | 2023-08-22 |
| 11728266 | Die stitching and harvesting of arrayed structures | Sanjay Dabral, Kunzhong Hu, Raymundo M. Camenforte | 2023-08-15 |
| 11699949 | Power management system switched capacitor voltage regulator with integrated passive device | Sanjay Dabral, David A. Secker, Ralf M. Schmitt, Vidhya Ramachandran, Wenjie Mao | 2023-07-11 |
| 11670548 | Structure and method for fabricating a computing system with an integrated voltage regulator module | Vidhya Ramachandran, Chonghua Zhong, Kunzhong Hu, Shawn Searles, Joseph T. DiBene, II +1 more | 2023-06-06 |
| 11646302 | Multiple chip module trenched lid and low coefficient of thermal expansion stiffener ring | Wei Chen, Jie Zhao, Po-Hao Chang, Hsien-Che Lin, Ying-Chieh Ke +1 more | 2023-05-09 |
| 11594494 | High density interconnection using fanout interposer chiplet | Chonghua Zhong, Kunzhong Hu | 2023-02-28 |