Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Sanjay Dabral — 128 Patents

Intel: 83 patents #286 of 30,777Top 1%
Apple: 38 patents #781 of 18,612Top 5%
RDRainbow Displays: 2 patents #12 of 22Top 55%
Cupertino, CA: #58 of 6,989 inventorsTop 1%
California: #1,392 of 386,348 inventorsTop 1%
Overall (All Time): #8,696 of 4,157,543Top 1%
128 Patents All Time
Sanjay Dabral has been granted 128 US patents while listed as an inventor at Intel. The first was granted in 1998 and the most recent in December 2025. Sanjay Dabral ranks #8,696 of 4,157,543 US inventors in our database (top 0.21%). Patent records list Sanjay Dabral in Cupertino, CA, US.

Issued Patents All Time

Showing 1–25 of 128 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12494468 3D system and wafer reconstitution with mid-layer interposer SivaChandra Jangam 2025-12-09
12469765 Thermally enhanced chip-on-wafer or wafer-on-wafer bonding Jinshu LU, Kui Hu, Jun Zhai 2025-11-11
12451436 Interconnecting a plurality of dies having spare input/output circuit Jun Zhai 2025-10-21
12424455 Seal ring designs supporting efficient die to die routing Chi Nung Ni, Long Huang, SivaChandra Jangam 2025-09-23
12322730 Wafer reconstitution and die-stitching Jun Zhai, Kwan-Yu Lai, Kunzhong Hu, Vidhya Ramachandran 2025-06-03
12261132 Structure and method for sealing a silicon IC Vidhya Ramachandran, SivaChandra Jangam, Jun Zhai, Kunzhong Hu 2025-03-25
12237269 Scalable large system based on organic interconnect Ravindranath Kollipara 2025-02-25
12176803 Decoupling device using stored charge reverse recovery Chi Nung Ni 2024-12-24 $240,476,000
12159835 High density 3D interconnect configuration Zhitao Cao, Kunzhong Hu, Jun Zhai 2024-12-03 $369,762,000
12119304 Very fine pitch and wiring density organic side by side chiplet integration Zhitao Cao, Kunzhong Hu 2024-10-15 $249,534,000
12087689 Selectable monolithic or external scalable die-to-die interconnection system methodology Jun Zhai, Jung-Cheng Yeh, Kunzhong Hu, Raymundo M. Camenforte, Thomas Hoffmann 2024-09-10 $233,602,000
12021035 Interconnecting dies by stitch routing Jun Zhai 2024-06-25 $209,077,000
11862557 Selectable monolithic or external scalable die-to-die interconnection system methodology Jun Zhai, Jung-Cheng Yeh, Kunzhong Hu, Raymundo M. Camenforte, Thomas Hoffmann 2024-01-02 $111,466,000
11862481 Seal ring designs supporting efficient die to die routing Chi Nung Ni, Long Huang, SivaChandra Jangam 2024-01-02 $111,466,000
11831312 Systems and methods for implementing a scalable system Bahattin Kilic, Jie Zhao, Kunzhong Hu, Suk-Kyu Ryu 2023-11-28 $171,025,000
11824015 Structure and method for sealing a silicon IC Vidhya Ramachandran, SivaChandra Jangam, Jun Zhai, Kunzhong Hu 2023-11-21 $128,924,000
11811303 Decoupling device using stored charge reverse recovery Chi Nung Ni 2023-11-07 $200,618,000
11735567 Wafer reconstitution and die-stitching Jun Zhai, Kwan-Yu Lai, Kunzhong Hu, Vidhya Ramachandran 2023-08-22 $159,607,000
11735526 High density 3D interconnect configuration Zhitao Cao, Kunzhong Hu, Jun Zhai 2023-08-22 $159,607,000
11728266 Die stitching and harvesting of arrayed structures Jun Zhai, Kunzhong Hu, Raymundo M. Camenforte 2023-08-15 $190,320,000
11699949 Power management system switched capacitor voltage regulator with integrated passive device David A. Secker, Jun Zhai, Ralf M. Schmitt, Vidhya Ramachandran, Wenjie Mao 2023-07-11 $274,907,000
11476203 Die-to-die routing through a seal ring Jun Zhai 2022-10-18 $195,408,000
11309895 Systems and methods for implementing a scalable system Bahattin Kilic, Jie Zhao, Kunzhong Hu, Suk-Kyu Ryu 2022-04-19 $219,368,000
11309246 High density 3D interconnect configuration Zhitao Cao, Kunzhong Hu, Jun Zhai 2022-04-19 $219,368,000
11158607 Wafer reconstitution and die-stitching Jun Zhai, Kwan-Yu Lai, Kunzhong Hu, Vidhya Ramachandran 2021-10-26 $273,635,000