Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
JH

Jun Chung Hsu — 22 Patents

Apple: 14 patents #2,362 of 18,612Top 15%
KTKinsus Interconnect Technology: 8 patents #6 of 37Top 20%
Cupertino, CA: #746 of 6,989 inventorsTop 15%
California: #25,951 of 386,348 inventorsTop 7%
Overall (All Time): #189,202 of 4,157,543Top 5%
22 Patents All Time
Jun Chung Hsu has been granted 22 US patents while listed as an inventor at Apple. The first was granted in 2010 and the most recent in June 2025. Jun Chung Hsu ranks #189,202 of 4,157,543 US inventors in our database (top 4.6%). Patent records list Jun Chung Hsu in Cupertino, CA, US.

Issued Patents All Time

Showing 1–22 of 22 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12322721 Asymmetric Stackup Structure for SoC package substrates Yikang Deng, Taegui Kim, Yifan Kao 2025-06-03
11908819 Semiconductor packaging substrate fine pitch metal bump and reinforcement structures Chih-Ming Chung, Jun Zhai, Yifan Kao, Young Doo Jeon, Taegui Kim 2024-02-20 $143,830,000
11862597 Asymmetric stackup structure for SoC package substrates Yikang Deng, Taegui Kim, Yifan Kao 2024-01-02 $111,466,000
11545455 Semiconductor packaging substrate fine pitch metal bump and reinforcement structures Chih-Ming Chung, Jun Zhai, Yifan Kao, Young Doo Jeon, Taegui Kim 2023-01-03 $247,903,000
10991659 Substrate-less integrated components Flynn Carson, Meng Chi Lee, Shatki S. Chauhan 2021-04-27 $300,345,000
10535611 Substrate-less integrated components Flynn Carson, Meng Chi Lee, Shakti Singh Chauhan 2020-01-14 $151,925,000
10522475 Vertical interconnects for self shielded system in package (SiP) modules Meng Chi Lee, Shakti Singh Chauhan, Flynn Carson, Tha-An Lin 2019-12-31 $109,024,000
10115677 Vertical interconnects for self shielded system in package (SiP) modules Meng Chi Lee, Shakti Singh Chauhan, Flynn Carson, Tha-An Lin 2018-10-30 $119,981,000
10109593 Self shielded system in package (SiP) modules Meng Chi Lee, Shakti Singh Chauhan, Flynn Carson, Tha-An Lin 2018-10-23 $108,278,000
9899239 Carrier ultra thin substrate Flynn Carson, Kwan-Yu Lai 2018-02-20 $98,367,000
9721903 Vertical interconnects for self shielded system in package (SiP) modules Meng Chi Lee, Shakti Singh Chauhan, Flynn Carson, Tha-An Lin 2017-08-01 $97,661,000
9633953 Methodology to achieve zero warpage for IC package Jie Zhao 2017-04-25 $59,408,000
9570367 Ultra fine pitch PoP coreless package Jun Zhai 2017-02-14 $78,066,000
9351409 Method of manufacturing a thin support package structure Hsueh-Ping Chien 2016-05-24
9305853 Ultra fine pitch PoP coreless package Jun Zhai 2016-04-05 $46,684,000
8837808 Method of final defect inspection Chia-Chi Lo, Cheng-Hsiung Yang 2014-09-16
8754328 Laminate circuit board with a multi-layer circuit structure Chi-Ming Lin, Tso-Hung Yeh, Ya-Hsiang Chen 2014-06-17
8547548 Final defect inspection system Chia-Chi Lo, Cheng-Hsiung Yang 2013-10-01
8315063 Solder pad structure with high bondability to solder ball 2012-11-20
7805835 Method for selectively processing surface tension of solder mask layer in circuit board Hsien-Ming Dai, Jen-Fang Chang 2010-10-05
7768131 Package structure preventing solder overflow on substrate solder pads Chen-Lin Li 2010-08-03
7662662 Method for manufacturing carrier substrate Bing-Kuen Lin, Chao-Lung Wang 2010-02-16