Issued Patents All Time
Showing 25 most recent of 45 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12266846 | System packaging for millimeter wave antennas | Sidharth Dalmia, Wansuk Yun | 2025-04-01 |
| 12165956 | Molded silicon on passive package | Kumar Nagarajan, Karthik Shanmugam, Menglu Li, Raymundo M. Camenforte, Scott D. Morrison | 2024-12-10 |
| 12107283 | Cell packaging techniques | Angelo V. Marasco, Nathan J. Bohney, John M. McCambridge, Antonio Manenti, Laura Mayer +2 more | 2024-10-01 |
| 12074077 | Flexible package architecture concept in fanout | Karthik Shanmugam, Jun Zhai, Raymundo M. Camenforte, Menglu Li | 2024-08-27 |
| 11395408 | Wafer-level passive array packaging | Scott D. Morrison, Karthik Shanmugam, Raymundo M. Camenforte, Rakshit Agrawal, Kiranjit Dhaliwal | 2022-07-19 |
| 10991659 | Substrate-less integrated components | Jun Chung Hsu, Meng Chi Lee, Shatki S. Chauhan | 2021-04-27 |
| 10643952 | Semiconductor device and method of forming EMI shielding layer with conductive material around semiconductor die | Reza A. Pagaila, Seung Uk Yoon | 2020-05-05 |
| 10631410 | Stacked printed circuit board packages | Corey S. Provencher, Meng Chi Lee, Derek Walters, Ian A. Spraggs, Shakti Singh Chauhan +9 more | 2020-04-21 |
| 10535611 | Substrate-less integrated components | Jun Chung Hsu, Meng Chi Lee, Shakti Singh Chauhan | 2020-01-14 |
| 10522475 | Vertical interconnects for self shielded system in package (SiP) modules | Meng Chi Lee, Shakti Singh Chauhan, Jun Chung Hsu, Tha-An Lin | 2019-12-31 |
| 10115677 | Vertical interconnects for self shielded system in package (SiP) modules | Meng Chi Lee, Shakti Singh Chauhan, Jun Chung Hsu, Tha-An Lin | 2018-10-30 |
| 10109593 | Self shielded system in package (SiP) modules | Meng Chi Lee, Shakti Singh Chauhan, Jun Chung Hsu, Tha-An Lin | 2018-10-23 |
| 9899239 | Carrier ultra thin substrate | Jun Chung Hsu, Kwan-Yu Lai | 2018-02-20 |
| 9721903 | Vertical interconnects for self shielded system in package (SiP) modules | Meng Chi Lee, Shakti Singh Chauhan, Jun Chung Hsu, Tha-An Lin | 2017-08-01 |
| 9679801 | Dual molded stack TSV package | Kwan-Yu Lai, Jun Zhai, Kunzhong Hu | 2017-06-13 |
| 9589936 | 3D integration of fanout wafer level packages | Jun Zhai, Kunzhong Hu | 2017-03-07 |
| 9484279 | Semiconductor device and method of forming EMI shielding layer with conductive material around semiconductor die | Reza A. Pagaila, Seung Uk Yoon | 2016-11-01 |
| 9331007 | Semiconductor device and method of forming conductive ink layer as interconnect structure between semiconductor packages | InSang Yoon, Il Kwon Shim, SeongHun Mun | 2016-05-03 |
| 9236319 | Stacked integrated circuit package system | Jong-Woo Ha, BumJoon Hong, Seongmin Lee | 2016-01-12 |
| 8723302 | Integrated circuit package system with input/output expansion | Harry Chandra | 2014-05-13 |
| 8598690 | Semiconductor device having conductive vias in peripheral region connecting shielding layer to ground | Harry Chandra | 2013-12-03 |
| 8409920 | Integrated circuit package system for package stacking and method of manufacture therefor | Rajendra D. Pendse, Il Kwon Shim, Seng Guan Chow | 2013-04-02 |
| 8241965 | Integrated circuit packaging system with pad connection and method of manufacture thereof | Henry Descalzo Bathan, Zigmund Ramirez Camacho, Emmanuel Espiritu | 2012-08-14 |
| 8129832 | Mountable integrated circuit package system with substrate having a conductor-free recess | In Sang Yoon, Seongmin Lee, JoHyun Bae | 2012-03-06 |
| 8110441 | Method of electrically connecting a shielding layer to ground through a conductive via disposed in peripheral region around semiconductor die | Harry Chandra | 2012-02-07 |