Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10345882 | Dynamic power meter with improved accuracy and single cycle resolution | Hugh Mair, Hsin-Chen Chen, Brian Flachs | 2019-07-09 |
| 9146772 | Reducing power grid noise in a processor while minimizing performance loss | Lee Evan Eisen, Michael Stephen Floyd, Thomas Strach, Tingdong Zhou | 2015-09-29 |
| 9141421 | Reducing power grid noise in a processor while minimizing performance loss | Lee Evan Eisen, Michael Stephen Floyd, Thomas Strach, Tingdong Zhou | 2015-09-22 |
| 9052905 | Minimizing power consumption for fixed-frequency processing unit operation | Malcolm S. Allen-Ware, Alan J. Drake, Wei Huang, Michael Stephen Floyd | 2015-06-09 |
| 8943341 | Minimizing power consumption for fixed-frequency processing unit operation | Malcolm S. Allen-Ware, Alan J. Drake, Wei Huang, Michael Stephen Floyd | 2015-01-27 |
| 8812879 | Processor voltage regulation | Joshua D. Friedrich, Norman K. James, Seongwon Kim, John R. Ripley, Edmund J. Sprogis | 2014-08-19 |
| 8180815 | Redundancy-free circuits for zero counters | Aleksandr Kaplun | 2012-05-15 |
| 7461110 | Redundancy-free circuits for zero counters | Aleksandr Kaplun | 2008-12-02 |
| 7206802 | Hybrid carry look ahead/carry select adder including carry logic generating complementary hot carry signals, and method for producing the carry logic | — | 2007-04-17 |
| 7024647 | System and method for designing a circuit wherein a single timing analysis ensures adequate performance in multiple applications | — | 2006-04-04 |
| 6718420 | Phase manipulation of intertwined bus signals for reduction of hostile coupling in integrated circuit interconnects | John T. Badar, John M. Isakson | 2004-04-06 |
| 6664836 | Dynamic phase splitter circuit and method for low-noise and simultaneous production of true and complement dynamic logic signals | — | 2003-12-16 |
| 6492856 | Edge triggered latch with symmetrical paths from clock to data outputs | Nobuo Kojima | 2002-12-10 |
| 6445217 | Edge-triggered latch with balanced pass-transistor logic trigger | Nobuo Kojima, Kevin John Nowka | 2002-09-03 |
| 6437625 | Edge triggered latch with symmetrical paths from clock to data outputs | Nobuo Kojima | 2002-08-20 |
| 6437624 | Edge-triggered latch with symmetric complementary pass-transistor logic data path | Nobuo Kojima | 2002-08-20 |
| 6407574 | Method and system for utilizing hostile-switching neighbors to improve interconnect speed for high performance processors | Hung C. Ngo | 2002-06-18 |
| 6085580 | Differential force microscope | Rudolf Ludeke | 2000-07-11 |