Issued Patents All Time
Showing 1–25 of 112 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10722729 | Probe for localized neural optogenetics stimulation and neurochemistry recordings | Hariklia Deligianni, Shu-Jen Han | 2020-07-28 |
| 10396665 | On-chip DC-DC power converters with fully integrated GaN power switches, silicon CMOS transistors and magnetic inductors | Hariklia Deligianni, Devendra K. Sadana, Naigang Wang | 2019-08-27 |
| 10134577 | Edge trim processes and resultant structures | Richard F. Indyk, Deepika Priyadarshini, Spyridon Skordas, Anthony K. Stamper, Kevin R. Winstel | 2018-11-20 |
| 10049909 | Wafer handler and methods of manufacture | John J. Garant, Jonathan H. Griffith, Brittany L. Hedrick | 2018-08-14 |
| 10032750 | Integrated DC-DC power converters through face-to-face bonding | Hariklia Deligianni, Devendra K. Sadana, Naigang Wang | 2018-07-24 |
| 9819269 | 3D integrated DC-DC power converters | Hariklia Deligianni, Devendra K. Sadana, Naigang Wang | 2017-11-14 |
| 9806615 | On-chip DC-DC power converters with fully integrated GaN power switches, silicon CMOS transistors and magnetic inductors | Hariklia Deligianni, Devendra K. Sadana, Naigang Wang | 2017-10-31 |
| 9654004 | 3D integrated DC-DC power converters | Hariklia Deligianni, Devendra K. Sadana, Naigang Wang | 2017-05-16 |
| 9613842 | Wafer handler and methods of manufacture | John J. Garant, Jonathan H. Griffith, Brittany L. Hedrick | 2017-04-04 |
| 9406562 | Integrated circuit and design structure having reduced through silicon via-induced stress | Jeffrey P. Bonn, Brent A. Goplen, Brian L. Kinsman, Robert M. Rassel, Daniel S. Vanslette | 2016-08-02 |
| 9385179 | Deep trench decoupling capacitor and methods of forming | James S. Nakos, Anthony K. Stamper | 2016-07-05 |
| 9368410 | Semiconductor devices having tensile and/or compressive stress and methods of manufacturing | Brent A. Anderson, Andres Bryant, Edward J. Nowak | 2016-06-14 |
| 9355936 | Flattened substrate surface for substrate bonding | Edward C. Cooney, III, James S. Dunn, Dale W. Martin, Charles S. Musante, BethAnn Rainey Lawrence +2 more | 2016-05-31 |
| 9331141 | CMOS structure on replacement substrate | Paul S. Andry, Cornelia K. Tsang | 2016-05-03 |
| 9111933 | Stacked through-silicon via (TSV) transformer structure | Gary Dale Carpenter, Alan J. Drake, Rachel Gordin, Michael J. Shapiro | 2015-08-18 |
| 9105627 | Coil inductor for on-chip or on-chip stack | Michael J. Shapiro, Gary Dale Carpenter, Alan J. Drake, Rachel Gordin | 2015-08-11 |
| 9040390 | Releasable buried layer for 3-D fabrication and methods of manufacturing | Timothy H. Daubenspeck, Steven E. Molis, Gordon C. Osborne, Jr., Wolfgang Sauter | 2015-05-26 |
| 8881379 | Method of making heat sink for integrated circuit devices | Douglas D. Coolbaugh, Ebenezer E. Eshun, Terence B. Hook, Robert M. Rassel, Anthony K. Stamper +1 more | 2014-11-11 |
| 8812879 | Processor voltage regulation | Huajun Wen, Joshua D. Friedrich, Norman K. James, Seongwon Kim, John R. Ripley | 2014-08-19 |
| 8785289 | Integrated decoupling capacitor employing conductive through-substrate vias | Tae Hong Kim, Michael F. McAllister, Michael J. Shapiro | 2014-07-22 |
| 8778737 | Flattened substrate surface for substrate bonding | Edward C. Cooney, III, James S. Dunn, Dale W. Martin, Charles F. Musante, BethAnn Rainey +2 more | 2014-07-15 |
| 8735251 | Through silicon via and method of fabricating same | Paul S. Andry, Cornelia K. Tsang | 2014-05-27 |
| 8637937 | Through silicon via for use in integrated circuit chips | Paul S. Andry, Cornelia K. Tsang | 2014-01-28 |
| 8631570 | Through wafer vias with dishing correction methods | Peter J. Lindgren, Anthony K. Stamper | 2014-01-21 |
| 8564113 | Electrostatic chucking of an insulator handle substrate | Paul S. Andry, Edward C. Cooney, III, Anthony K. Stamper, Cornelia K. Tsang | 2013-10-22 |