Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9040390 | Releasable buried layer for 3-D fabrication and methods of manufacturing | Timothy H. Daubenspeck, Steven E. Molis, Wolfgang Sauter, Edmund J. Sprogis | 2015-05-26 |
| 6603195 | Planarized plastic package modules for integrated circuits | David V. Caletka, James L. Carper, John P. Cincotta, Kibby B. Horsford, Gary H. Irish +4 more | 2003-08-05 |
| 5672980 | Method and apparatus for testing integrated circuit chips | Richard Gordon Charlton, George C. Correia, Mark Andrew Couture, Gary R. Hill, Kibby B. Horsford +4 more | 1997-09-30 |
| 5659256 | Method and apparatus for testing integrated circuit chips | Richard Gordon Charlton, George C. Correia, Mark Andrew Couture, Gary R. Hill, Kibby B. Horsford +4 more | 1997-08-19 |
| 5528159 | Method and apparatus for testing integrated circuit chips | Richard Gordon Charlton, George C. Correia, Mark Andrew Couture, Gary R. Hill, Kibby B. Horsford +4 more | 1996-06-18 |
| 5523696 | Method and apparatus for testing integrated circuit chips | Richard Gordon Charlton, George C. Correla, Mark Andrew Couture, Gary R. Hill, Kibby B. Horsford +4 more | 1996-06-04 |
| 4907734 | Method of bonding gold or gold alloy wire to lead tin solder | H. Ward Conru, Stephen E. Gons, Douglas W. Phelps, Jr., Stephen G. Starr, William Ward | 1990-03-13 |