Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10304763 | Producing wafer level packaging using leadframe strip and related device | Richard S. Graf, Sudeep Mandal | 2019-05-28 |
| 9892999 | Producing wafer level packaging using leadframe strip and related device | Richard S. Graf, Sudeep Mandal | 2018-02-13 |
| 9496234 | Wafer-level chip-scale package structure utilizing conductive polymer | Richard S. Graf, Sudeep Mandal | 2016-11-15 |
| 7670437 | Mask and substrate alignment for solder bump process | Duane Edward Allen, Brian K. Burnor, Thomas A. Dotolo, Leonard Gardecki, William L. Hammond +1 more | 2010-03-02 |
| 7410919 | Mask and substrate alignment for solder bump process | Duane Edward Allen, Brian K. Burnor, Thomas A. Dotolo, Leonard Gardecki, William L. Hammond +1 more | 2008-08-12 |
| 6603195 | Planarized plastic package modules for integrated circuits | David V. Caletka, James L. Carper, John P. Cincotta, Gary H. Irish, John J. Lajza, Jr. +4 more | 2003-08-05 |
| 5672980 | Method and apparatus for testing integrated circuit chips | Richard Gordon Charlton, George C. Correia, Mark Andrew Couture, Gary R. Hill, Anthony P. Ingraham +4 more | 1997-09-30 |
| 5659256 | Method and apparatus for testing integrated circuit chips | Richard Gordon Charlton, George C. Correia, Mark Andrew Couture, Gary R. Hill, Anthony P. Ingraham +4 more | 1997-08-19 |
| 5528159 | Method and apparatus for testing integrated circuit chips | Richard Gordon Charlton, George C. Correia, Mark Andrew Couture, Gary R. Hill, Anthony P. Ingraham +4 more | 1996-06-18 |
| 5523696 | Method and apparatus for testing integrated circuit chips | Richard Gordon Charlton, George C. Correla, Mark Andrew Couture, Gary R. Hill, Anthony P. Ingraham +4 more | 1996-06-04 |