| 6414509 |
Method and apparatus for in-situ testing of integrated circuit chips |
Anilkumar C. Bhatt, Leo Raymond Buda, Robert D. Edwards, Paul Joseph Hart, Voya R. Markovich +6 more |
2002-07-02 |
| 6256203 |
Free standing, three dimensional, multi-chip, carrier package with air flow baffle |
Glenn L. Kehley, Sanjeev Sathe, John R. Slack |
2001-07-03 |
| 6150255 |
Method of planarizing a curved substrate and resulting structure |
Francis J. Downes, Jr., Stephen Joseph Fuerniss, Gary R. Hill, Voya R. Markovich, Jaynal A. Molla |
2000-11-21 |
| 6121069 |
Interconnect structure for joining a chip to a circuit card |
Christina M. Boyko, Voya R. Markovich, David J. Russell |
2000-09-19 |
| 6094059 |
Apparatus and method for burn-in/testing of integrated circuit devices |
Jerome A. Frankeny, James Steven Kamperman, James R. Wilcox |
2000-07-25 |
| 6094060 |
Test head for applying signals in a burn-in test of an integrated circuit |
Jerome A. Frankeny, James Steven Kamperman, James R. Wilcox |
2000-07-25 |
| 6075287 |
Integrated, multi-chip, thermally conductive packaging device and methodology |
Glenn L. Kehley, Sanjeev Sathe, John R. Slack |
2000-06-13 |
| 6061245 |
Free standing, three dimensional, multi-chip, carrier package with air flow baffle |
Glenn L. Kehley, Sanjeev Sathe, John R. Slack |
2000-05-09 |
| 5994910 |
Apparatus, and corresponding method, for stress testing wire bond-type semi-conductor chips |
Francis J. Downes, Jr., Jaynal A. Molla |
1999-11-30 |
| 5953623 |
Ball limiting metal mask and tin enrichment of high melting point solder for low temperature interconnection |
Christina M. Boyko, Voya R. Markovich, David J. Russell |
1999-09-14 |
| 5949246 |
Test head for applying signals in a burn-in test of an integrated circuit |
Jerome A. Frankeny, James Steven Kamperman, James R. Wilcox |
1999-09-07 |
| 5940729 |
Method of planarizing a curved substrate and resulting structure |
Francis J. Downes, Jr., Stephen Joseph Fuerniss, Gary R. Hill, Voya R. Markovich, Jaynal A. Molla |
1999-08-17 |
| 5926369 |
Vertically integrated multi-chip circuit package with heat-sink support |
Glenn L. Kehley, Sanjeev Sathe, John R. Slack |
1999-07-20 |
| 5759046 |
Dendritic interconnection system |
Jaynal A. Molla, David B. Stone |
1998-06-02 |
| 5709336 |
Method of forming a solderless electrical connection with a wirebond chip |
William T. Chen |
1998-01-20 |
| 5672980 |
Method and apparatus for testing integrated circuit chips |
Richard Gordon Charlton, George C. Correia, Mark Andrew Couture, Gary R. Hill, Kibby B. Horsford +4 more |
1997-09-30 |
| 5659256 |
Method and apparatus for testing integrated circuit chips |
Richard Gordon Charlton, George C. Correia, Mark Andrew Couture, Gary R. Hill, Kibby B. Horsford +4 more |
1997-08-19 |
| 5528159 |
Method and apparatus for testing integrated circuit chips |
Richard Gordon Charlton, George C. Correia, Mark Andrew Couture, Gary R. Hill, Kibby B. Horsford +4 more |
1996-06-18 |
| 5523696 |
Method and apparatus for testing integrated circuit chips |
Richard Gordon Charlton, George C. Correla, Mark Andrew Couture, Gary R. Hill, Kibby B. Horsford +4 more |
1996-06-04 |
| 5420520 |
Method and apparatus for testing of integrated circuit chips |
Morris Anschel, Charles Robert Lamb, Michael D. Lowell, Voya R. Markovich, Wolfgang Mayr +7 more |
1995-05-30 |
| 5391514 |
Low temperature ternary C4 flip chip bonding method |
Thomas P. Gall |
1995-02-21 |
| 5185073 |
Method of fabricating nendritic materials |
Perminder S. Bindra, Jerome J. Cuomo, Thomas P. Gall, Sung Kwon Kang, Jungihl Kim +10 more |
1993-02-09 |
| 5137461 |
Separable electrical connection technology |
Perminder S. Bindra, Jerome J. Cuomo, Thomas P. Gall, Sung Kwon Kang, Jungihl Kim +10 more |
1992-08-11 |
