Issued Patents All Time
Showing 25 most recent of 45 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7510324 | Method of inspecting articles using imaging inspection apparatus with directional cooling | Ashwinkumar C. Bhatt, Varaprasad V. Calmidi, James J. McNamara, Jr. | 2009-03-31 |
| 7510912 | Method of making wirebond electronic package with enhanced chip pad design | David V. Caletka, Varaprasad V. Calmidi | 2009-03-31 |
| 7490984 | Method of making an imaging inspection apparatus with improved cooling | Ashwinkumar C. Bhatt, Varaprasad V. Calmidi, James J. McNamara, Jr. | 2009-02-17 |
| 7354197 | Imaging inspection apparatus with improved cooling | Ashwinkumar C. Bhatt, Varaprasad V. Calmidi, James J. McNamara, Jr. | 2008-04-08 |
| 7348261 | Wafer scale thin film package | David V. Caletka, Seungbae Park | 2008-03-25 |
| 7261466 | Imaging inspection apparatus with directional cooling | Ashwinkumar C. Bhatt, Varaprasad V. Calmidi, James J. McNamara, Jr. | 2007-08-28 |
| 7253518 | Wirebond electronic package with enhanced chip pad design, method of making same, and information handling system utilizing same | David V. Caletka, Varaprasad V. Calmidi | 2007-08-07 |
| 7186590 | Thermally enhanced lid for multichip modules | David J. Alcoe, William L. Brodsky, Varaprasad V. Calmidi, Randall J. Stutzman | 2007-03-06 |
| 7183642 | Electronic package with thermally-enhanced lid | Anandaroop Bhattacharya, Varaprasad V. Calmidi | 2007-02-27 |
| 7037753 | Non-planar surface for semiconductor chips | William L. Brodsky, George H. Thiel | 2006-05-02 |
| 7026706 | Method and packaging structure for optimizing warpage of flip chip organic packages | William Infantolino, Li Li, Steven G. Rosser | 2006-04-11 |
| 6992379 | Electronic package having a thermal stretching layer | David J. Alcoe, Li Li | 2006-01-31 |
| 6989607 | Stress reduction in flip-chip PBGA packaging by utilizing segmented chips and/or chip carriers | Krishna Darbha, Miguel A. Jimarez, Matthew Reiss, Charles G. Woychik | 2006-01-24 |
| 6967389 | Wafer with semiconductor chips mounted thereon | William Infantolino, Voya R. Markovich, George H. Thiel | 2005-11-22 |
| 6788859 | Laminate substrate containing fiber optic cables | Voya R. Markovich, Sandeep B. Sane | 2004-09-07 |
| 6759270 | Semiconductor chip module and method of manufacture of same | William Infantolino, Voya R. Markovich, George H. Thiel | 2004-07-06 |
| 6756662 | Semiconductor chip module and method of manufacture of same | William Infantolino, Voya R. Markovich, George H. Thiel | 2004-06-29 |
| 6747331 | Method and packaging structure for optimizing warpage of flip chip organic packages | William Infantolino, Li Li, Steven G. Rosser | 2004-06-08 |
| 6731012 | Non-planar surface for semiconductor chips | William L. Brodsky, George H. Thiel | 2004-05-04 |
| 6665187 | Thermally enhanced lid for multichip modules | David J. Alcoe, William L. Brodsky, Varaprasad V. Calmidi, Randall J. Stutzman | 2003-12-16 |
| 6639302 | Stress reduction in flip-chip PBGA packaging by utilizing segmented chip carries | Krishna Darbha, Miguel A. Jimarez, Matthew Reiss, Charles G. Woychik | 2003-10-28 |
| 6631078 | Electronic package with thermally conductive standoff | David J. Alcoe, Varaprasad V. Calmidi, Krishna Darbha | 2003-10-07 |
| 6627998 | Wafer scale thin film package | David V. Caletka, Seungbae Park | 2003-09-30 |
| 6622786 | Heat sink structure with pyramidic and base-plate cut-outs | Varaprasad V. Calmidi, Krishna Darbha, Jamil A. Wakil | 2003-09-23 |
| 6347901 | Solder interconnect techniques | Seungbae Park, Aleksander Zubelewicz | 2002-02-19 |