Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Sandeep B. Sane — 30 Patents

Intel: 28 patents #1,370 of 30,777Top 5%
LILightmatter: 1 patents #31 of 50Top 65%
IBM: 1 patents #44,878 of 70,183Top 65%
Chandler, AZ: #155 of 3,331 inventorsTop 5%
Arizona: #984 of 32,909 inventorsTop 3%
Overall (All Time): #121,623 of 4,157,543Top 3%
30 Patents All Time
Sandeep B. Sane has been granted 30 US patents while listed as an inventor at Intel. The first was granted in 2004 and the most recent in July 2025. Sandeep B. Sane ranks #121,623 of 4,157,543 US inventors in our database (top 2.9%). Patent records list Sandeep B. Sane in Chandler, AZ, US.

Patents per Year

Patents granted per year, 2004 to 2025Bar chart with a peak of 3 patents in 2007.peak 32004: 1 patents20042005: 1 patents2007: 3 patents20072009: 1 patents2010: 1 patents20102011: 2 patents2012: 1 patents20122013: 1 patents2015: 2 patents20152016: 2 patents2017: 2 patents20172018: 1 patents2019: 1 patents20192020: 2 patents2022: 2 patents20222023: 2 patents2024: 3 patents20242025: 2 patents2025

Issued Patents All Time

Showing 1–25 of 30 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12355492 Spectrally interleaved optical transceivers Kuang Liu, Binoy Shah, Jessie C. Rosenberg, Nikhil Kumar, Anthony Kopa +6 more 2025-07-08
12347783 Interconnect architecture with silicon interposer and EMIB MD Altaf Hossain, Ankireddy Nalamalpu, Dheeraj Subbareddy, Robert Sankman, Ravindranath V. Mahajan +7 more 2025-07-01
12038858 Processor package with universal optical input/output Anshuman Thakur, Dheeraj Subareddy, MD Altaf Hossain, Ankireddy Nalamalpu, Mahesh Kumashikar 2024-07-16 $26,089,000
11983135 Electrical and optical interfaces at different heights along an edge of a package to increase bandwidth along the edge Dheeraj Subbareddy, Ankireddy Nalamalpu, Anshuman Thakur, MD Altaf Hossain, Mahesh Kumashikar +3 more 2024-05-14 $33,809,000
11901299 Interconnect architecture with silicon interposer and EMIB MD Altaf Hossain, Ankireddy Nalamalpu, Dheeraj Subbareddy, Robert Sankman, Ravindranath V. Mahajan +7 more 2024-02-13 $18,546,000
11824013 Package substrate with reduced interconnect stress Lauren A. Link, Andrew J. Brown, Sheng Li 2023-11-21 $28,968,000
11557541 Interconnect architecture with silicon interposer and EMIB MD Altaf Hossain, Ankireddy Nalamalpu, Dheeraj Subbareddy, Robert Sankman, Ravindranath V. Mahajan +7 more 2023-01-17 $13,997,000
11417592 Methods of utilizing low temperature solder assisted mounting techniques for package structures Omkar G. Karhade, Nachiket R. Raravikar 2022-08-16 $17,788,000
11276625 Methods of forming flexure based cooling solutions for package structures Siddarth Kumar, Shubhada H. Sahasrabudhe, Shalabh Tandon 2022-03-15 $18,336,000
10811366 Microelectronic bond pads having integrated spring structures Feras Eid, Robert L. Sankman 2020-10-20 $43,271,000
10531575 Systems and methods for replaceable bail grid array (BGA) packages on board substrates Timothy Swettlen 2020-01-07 $22,293,000
10325860 Microelectronic bond pads having integrated spring structures Feras Eid, Robert L. Sankman 2019-06-18 $21,210,000
9953934 Warpage controlled package and method for same Siddarth Kumar, Shubhada H. Sahasrabudhe, Shalabh Tandon 2018-04-24 $19,097,000
9659899 Die warpage control for thin die assembly Shankar Ganapathysubramanian, Jorge Sanchez, Leonel Arana, Eric J. Li, Nitin A. Deshpande +2 more 2017-05-23 $7,972,000
9659908 Systems and methods for package on package through mold interconnects Shubhada H. Sahasrabudhe, Siddarth Kumar, Shalabh Tandon 2017-05-23 $7,972,000
9394619 Methods of adding dopants to conductive interconnect structures in substrate technologies and structures formed thereby Rajen S. Sidhu, Mukul Renavikar 2016-07-19 $7,217,000
9368461 Contact pads for integrated circuit packages Sven Albers, Georg Seidemann, Sonja Koller, Stephan Stoeckl, Shubhada H. Sahasrabudhe 2016-06-14 $9,885,000
9123732 Die warpage control for thin die assembly Shankar Ganapathysubramanian, Jorge Sanchez, Leonel Arana, Eric J. Li, Nitin A. Deshpande +2 more 2015-09-01 $13,376,000
8941236 Using collapse limiter structures between elements to reduce solder bump bridging Ameya Limaye, Richard J. Harries 2015-01-27 $21,987,000
8441809 Microelectronic package containing silicon connecting region for high density interconnects, and method of manufacturing same Ravi Mahajan 2013-05-14 $17,697,000
8324737 Modified chip attach process Biju Chandran 2012-12-04 $14,359,000
8064224 Microelectronic package containing silicon patches for high density interconnects, and method of manufacturing same Ravi Mahajan 2011-11-22 $16,463,000
7901982 Modified chip attach process Biju Chandran 2011-03-08 $15,954,000
7781260 Methods of forming nano-coatings for improved adhesion between first level interconnects and epoxy under-fills in microelectronic packages and structures formed thereby Nachiket R. Raravikar 2010-08-24 $13,244,000
7579213 Modified chip attach process Biju Chandran 2009-08-25 $20,594,000