| 12429900 |
Controlled transition between configuration mode and user mode to reduce current-resistance voltage drop |
Atul Maheshwari, Ankireddy Nalamalpu, Mahesh A. Iyer |
2025-09-30 |
| 12431899 |
Self-gating flops for dynamic power reduction |
MD Altaf Hossain, Yuet-Wing Li, Atul Maheshwari, Ankireddy Nalamalpu |
2025-09-30 |
| 12422477 |
Segmented row repair for programmable logic devices |
Dheeraj Subbareddy, Arun Jangity, Ramya Yeluri, Atul Maheshwari, Ankireddy Nalamalpu |
2025-09-23 |
| 12379698 |
Systems and methods to reduce voltage guardband |
MD Altaf Hossain, Mahesh A. Iyer, Yuet-Wing Li, Atul Maheshwari, Ankireddy Nalamalpu |
2025-08-05 |
| 12355359 |
Switch based on load current |
MD Altaf Hossain, Ankireddy Nalamalpu, Dheeraj Subbareddy, Atul Maheshwari, Mahesh A. Iyer |
2025-07-08 |
| 12353238 |
Flexible instruction set architecture supporting varying frequencies |
Dheeraj Subbareddy, Anshuman Thakur, Atul Maheshwari, MD Altaf Hossain, Ankireddy Nalamalpu |
2025-07-08 |
| 12341511 |
Power management using voltage islands on programmable logic devices |
Ankireddy Nalamalpu, MD Altaf Hossain, Dheeraj Subbareddy, Atul Maheshwari, Yuet-Wing Li +1 more |
2025-06-24 |
| 12334449 |
Selective use of different advanced interface bus with electronic chips |
Dheeraj Subbareddy, Ankireddy Nalamalpu, Lai Guan Tang |
2025-06-17 |
| 12321714 |
Compressed wallace trees in FMA circuits |
Aditya Varma, Michael Espig |
2025-06-03 |
| 12294368 |
Three-dimensional stacked programmable logic fabric and processor design architecture |
Rahul Pal, Dheeraj Subbareddy, Dheemanth Nagaraj, Rajesh Vivekanandham, Anshuman Thakur +3 more |
2025-05-06 |
| 12273107 |
Dynamically scalable timing and power models for programmable logic devices |
Atul Maheshwari, Mahesh A. Iyer, Ian Kuon, Yuet-Wing Li, Ankireddy Nalamalpu +1 more |
2025-04-08 |
| 12038858 |
Processor package with universal optical input/output |
Anshuman Thakur, Dheeraj Subareddy, MD Altaf Hossain, Ankireddy Nalamalpu, Sandeep B. Sane |
2024-07-16 |
| 12007929 |
Low-latency optical connection for CXL for a server CPU |
Anshuman Thakur, Dheeraj Subbareddy, MD Altaf Hossain, Ankireddy Nalamalpu |
2024-06-11 |
| 11983135 |
Electrical and optical interfaces at different heights along an edge of a package to increase bandwidth along the edge |
Dheeraj Subbareddy, Ankireddy Nalamalpu, Anshuman Thakur, MD Altaf Hossain, Kemal Aygun +3 more |
2024-05-14 |
| 11899615 |
Multiple dies hardware processors and methods |
Nevine Nassif, Yen-Cheng Liu, Krishnakanth V. Sistla, Gerald Pasdast, Siva Soumya Eachempati +10 more |
2024-02-13 |
| 11757434 |
High performance fast Mux-D scan flip-flop |
Amit Agarwal, Steven Hsu, Simeon Realov, Ram Krishnamurthy |
2023-09-12 |
| 11734174 |
Low overhead, high bandwidth re-configurable interconnect apparatus and method |
Huichu Liu, Tanay Karnik, Tejpal Singh, Yen-Cheng Liu, Lavanya Subramanian +6 more |
2023-08-22 |
| 11586579 |
Multiple dies hardware processors and methods |
Nevine Nassif, Yen-Cheng Liu, Krishnakanth V. Sistla, Gerald Pasdast, Siva Soumya Eachempati +10 more |
2023-02-21 |
| 11296681 |
High performance fast Mux-D scan flip-flop |
Amit Agarwal, Steven Hsu, Simeon Realov, Ram Krishnamurthy |
2022-04-05 |
| 11294852 |
Multiple dies hardware processors and methods |
Nevine Nassif, Yen-Cheng Liu, Krishnakanth V. Sistla, Gerald Pasdast, Siva Soumya Eachempati +10 more |
2022-04-05 |
| 10795853 |
Multiple dies hardware processors and methods |
Nevine Nassif, Yen-Cheng Liu, Krishnakanth V. Sistla, Gerald Pasdast, Siva Soumya Eachempati +10 more |
2020-10-06 |
| 9552308 |
Early wake-warn for clock gating control |
Suresh Sugumar, Rahul Pal, Sridhar Muthrasanallur |
2017-01-24 |
| 9229879 |
Power reduction using unmodified information in evicted cache lines |
Ashok Jagannathan |
2016-01-05 |