Issued Patents All Time
Showing 25 most recent of 64 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12386618 | Multi-buffered register files with shared access circuits | Amit Agarwal, Debabrata Mohapatra, Arnab Raha, Moongon Jung, Gautham Chinya +1 more | 2025-08-12 |
| 12243148 | Apparatus and method for approximate trilinear interpolation for scene reconstruction | Vivek K. De, Ram Krishnamurthy, Amit Agarwal, Monodeep Kar | 2025-03-04 |
| 12223615 | Apparatus and method for approximate trilinear interpolation for scene reconstruction | Vivek K. De, Ram Krishnamurthy, Amit Agarwal, Monodeep Kar | 2025-02-11 |
| 11791819 | Low power flip-flop with reduced parasitic capacitance | Amit Agarwal, Simeon Realov, Ram Krishnamurthy | 2023-10-17 |
| 11757434 | High performance fast Mux-D scan flip-flop | Amit Agarwal, Simeon Realov, Mahesh Kumashikar, Ram Krishnamurthy | 2023-09-12 |
| 11442103 | Multibit vectored sequential with scan | Amit Agarwal, Ram Krishnamurthy, Satish K. Damaraju, Simeon Realov | 2022-09-13 |
| 11398814 | Low-power single-edge triggered flip-flop, and time borrowing internally stitched flip-flop | Amit Agarwal, Simeon Realov, Satish K. Damaraju, Ram Krishnamurthy | 2022-07-26 |
| 11296681 | High performance fast Mux-D scan flip-flop | Amit Agarwal, Simeon Realov, Mahesh Kumashikar, Ram Krishnamurthy | 2022-04-05 |
| 11054470 | Double edge triggered Mux-D scan flip-flop | Amit Agarwal, Anupama A. Thaploo, Simeon Realov, Ram Krishnamurthy | 2021-07-06 |
| 11009549 | Multibit vectored sequential with scan | Amit Agarwal, Ram Krishnamurthy, Satish K. Damaraju, Simeon Realov | 2021-05-18 |
| 10862462 | Vectored flip-flop | Amit Agarwal, Simeon Realov | 2020-12-08 |
| 10756736 | Fused voltage level shifting latch | Amit Agarwal, Ram Krishnamurthy | 2020-08-25 |
| 10498314 | Vectored flip-flop | Amit Agarwal, Simeon Realov | 2019-12-03 |
| 10491217 | Low-power clock gate circuit | Amit Agarwal, Simeon Realov, Iqbal Rajwani, Ram Krishnamurthy | 2019-11-26 |
| 10473718 | Multibit vectored sequential with scan | Amit Agarwal, Ram Krishnamurthy, Satish K. Damaraju, Simeon Realov | 2019-11-12 |
| 10418975 | Low clock supply voltage interruptible sequential | Amit Agarwal, Ram Krishnamurthy | 2019-09-17 |
| 10382019 | Time borrowing flip-flop with clock gating scan multiplexer | Amit Agarwal, Simeon Realov, Ram Krishnamurthy | 2019-08-13 |
| 10193536 | Shared keeper and footer flip-flop | Amit Agarwal, Simeon Realov, Iqbal Rajwani, Ram Krishnamurthy | 2019-01-29 |
| 10177765 | Integrated clock gate circuit with embedded NOR | Amit Agarwal, Iqbal Rajwani, Simeon Realov, Ram Krishnamurthy | 2019-01-08 |
| 10049724 | Aging tolerant register file | Amit Agarwal, Sri Harsha Choday | 2018-08-14 |
| 9985612 | Time borrowing flip-flop with clock gating scan multiplexer | Amit Agarwal, Simeon Realov, Ram Krishnamurthy | 2018-05-29 |
| 9960753 | Apparatus and method for low power fully-interruptible latches and master-slave flip-flops | Amit Agarwal, Ram Krishnamurthy | 2018-05-01 |
| 9859876 | Shared keeper and footer flip-flop | Amit Agarwal, Simeon Realov, Iqbal Rajwani, Ram Krishnamurthy | 2018-01-02 |
| 9641160 | Common N-well state retention flip-flop | Amit Agarwal, Ram Krishnamurthy | 2017-05-02 |
| 9397641 | Apparatus and method for low power fully-interruptible latches and master-slave flip-flops | Amit Agarwal, Ram Krishnamurthy | 2016-07-19 |