Issued Patents All Time
Showing 51–64 of 64 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6844750 | Current mirror based multi-channel leakage current monitor circuit and method | Ram Krishnamurthy, Chris Hyung-il Kim | 2005-01-18 |
| 6781892 | Active leakage control in single-ended full-swing caches | Sanu K. Mathew, Ram Krishnamurthy | 2004-08-24 |
| 6762957 | Low clock swing latch for dual-supply voltage design | Bhaskar P. Chatterjee, Ram Krishnamurthy | 2004-07-13 |
| 6749465 | Card connector with reinforcing structure | Che-Hung Huang | 2004-06-15 |
| 6707708 | Static random access memory with symmetric leakage-compensated bit line | Atila Alvandpour, Dinesh Somasekhar, Ram Krishnamurthy, Vivek K. De | 2004-03-16 |
| 6693461 | Multiple supply-voltage zipper CMOS logic family with low active leakage power dissipation | Ram Krishnamurthy | 2004-02-17 |
| 6690604 | Register files and caches with digital sub-threshold leakage current calibration | Shih-Lien Linus Lu, Ram Krishnamurthy | 2004-02-10 |
| 6643199 | Memory with reduced sub-threshold leakage current in dynamic bit lines of read ports | Stephen H. Tang, Vivek K. De, Shih-Lien Linus Lu | 2003-11-04 |
| 6628557 | Leakage-tolerant memory arrangements | Ram Krishnamurthy | 2003-09-30 |
| 6628143 | Full-swing source-follower leakage tolerant dynamic logic | Mark A. Anders, Sanu K. Mathew, Ram Krishnamurthy | 2003-09-30 |
| 6618316 | Pseudo-static single-ended cache cell | Ram Krishnamurthy | 2003-09-09 |
| 6563357 | Level converting latch | Bhaskar P. Chatterjee, Ram Krishnamurthy | 2003-05-13 |
| 6441648 | Double data rate dynamic logic | Shih-Lien Linus Lu, Ram Krishnamurthy | 2002-08-27 |
| 6404234 | Variable virtual ground domino logic with leakage control | Sanu K. Mathew, Ram Krishnamurthy | 2002-06-11 |