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Multi-buffered register files with shared access circuits |
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Sparsity-aware datastore for inference processing in deep neural network architectures |
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Schedule-aware dynamically reconfigurable adder tree architecture for partial sum accumulation in machine learning accelerators |
Debabrata Mohapatra, Deepak Abraham Mathaikutty, Raymond Jit-Hung Sung, Cormac Brick |
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Performance scaling for dataflow deep neural network hardware accelerators |
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Methods and apparatus to load data within a machine learning accelerator |
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Schedule-aware tensor distribution module |
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System architecture and method of processing data therein |
Vijay Raghunathan |
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Lightweight trusted execution for internet-of-things devices |
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Microcontroller energy management system |
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