| 12367380 |
System and method for balancing sparsity in weights for accelerating deep neural networks |
Arnab Raha, Debabrata Mohapatra, Deepak Abraham Mathaikutty, Cormac Brick |
2025-07-22 |
| 12229673 |
Sparsity-aware datastore for inference processing in deep neural network architectures |
Deepak Abraham Mathaikutty, Arnab Raha, Debabrata Mohapatra, Cormac Brick |
2025-02-18 |
| 12147836 |
Schedule-aware dynamically reconfigurable adder tree architecture for partial sum accumulation in machine learning accelerators |
Debabrata Mohapatra, Arnab Raha, Deepak Abraham Mathaikutty, Cormac Brick |
2024-11-19 |
| 12141683 |
Performance scaling for dataflow deep neural network hardware accelerators |
Arnab Raha, Debabrata Mohapatra, Gautham Chinya, Guruguhanathan Venkataramanan, Sang Kyun Kim +2 more |
2024-11-12 |
| 8477556 |
Memory architecture having multiple partial wordline drivers and contacted and feed-through bitlines |
Dongwook Suh, Daniel Rodriguez |
2013-07-02 |
| 8009506 |
Memory architecture having multiple partial wordline drivers and contacted and feed-through bitlines |
Dongwook Suh, Daniel Rodriguez |
2011-08-30 |
| 7697364 |
Memory architecture having multiple partial wordline drivers and contacted and feed-through bitlines |
Dongwook Suh, Daniel Rodriguez |
2010-04-13 |
| 7123056 |
Clock logic domino circuits for high-speed and energy efficient microprocessor pipelines |
Duncan George Elliott |
2006-10-17 |
| 7046522 |
Method for scalable architectures in stackable three-dimensional integrated circuits and electronics |
Tyler Lee Brandon, John Conrad Koob, Duncan George Elliott, Daniel Arie Leder |
2006-05-16 |
| 6806737 |
Bi-directional amplifier and method for accelerated bus line communication |
John Conrad Koob, Tyler Lee Brandon, Duncan George Elliot |
2004-10-19 |
| 6803782 |
Arrayed processing element redundancy architecture |
John Conrad Koob, Tyler Lee Brandon, Duncan George Elliot |
2004-10-12 |