Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8502317 | Level shifter circuits for integrated circuits | Leendert Jan van den Berg | 2013-08-06 |
| 8462574 | Memory sensing with secondary buffer | Kristopher Breen | 2013-06-11 |
| 8027212 | Method and apparatus for a dynamic semiconductor memory with compact sense amplifier circuit | Kristopher Breen | 2011-09-27 |
| 7936192 | Alias-locked loop frequency synthesizer using a regenerative sampling latch | Leendert Jan van den Berg | 2011-05-03 |
| 7215563 | Multi-layered memory cell structure | Tyler Lee Brandon | 2007-05-08 |
| 7155581 | Method and apparatus for an energy efficient operation of multiple processors in a memory | W. Martin Snelgrove | 2006-12-26 |
| 7123056 | Clock logic domino circuits for high-speed and energy efficient microprocessor pipelines | Raymond Jit-Hung Sung | 2006-10-17 |
| 7046522 | Method for scalable architectures in stackable three-dimensional integrated circuits and electronics | Raymond Jit-Hung Sung, Tyler Lee Brandon, John Conrad Koob, Daniel Arie Leder | 2006-05-16 |
| 6560684 | Method and apparatus for an energy efficient operation of multiple processors in a memory | W. Martin Snelgrove | 2003-05-06 |
| 6556469 | System and method for multilevel DRAM sensing and restoring | Gershom Birk, Bruce Cockburn | 2003-04-29 |
| 6279088 | Memory device with multiple processors having parallel access to the same memory area | W. Martin Snelgrove | 2001-08-21 |
| 5956274 | Memory device with multiple processors having parallel access to the same memory area | W. Martin Snelgrove | 1999-09-21 |
| 5546343 | Method and apparatus for a single instruction operating multiple processors on a memory chip | W. Martin Snelgrove | 1996-08-13 |