Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Schedule-aware dynamically reconfigurable adder tree architecture for partial sum accumulation in machine learning accelerators

Schedule-aware dynamically reconfigurable adder tree architecture for partial sum accumulation in machine learning accelerators

US Patent 12147836 · Granted Nov 19, 2024

Estimated economic value: $25,575,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Methods, systems, articles of manufacture, and apparatus to decode zero-value-co2025
Methods, systems, articles of manufacture, and apparatus to decode zero-value-co2025
Methods, systems, articles of manufacture, and apparatus to decode zero-value-co2025
Methods and apparatus for sparse tensor storage for neural network accelerators2025
Multi-buffered register files with shared access circuits2025
Multi-buffered register files with shared access circuits2025
System and method for balancing sparsity in weights for accelerating deep neural2025
System and method for balancing sparsity in weights for accelerating deep neural2025
System and method for balancing sparsity in weights for accelerating deep neural2025
System and method for balancing sparsity in weights for accelerating deep neural2025
System and method for balancing sparsity in weights for accelerating deep neural2025
Schedule-aware tensor distribution module2025