Issued Patents All Time
Showing 25 most recent of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12288153 | Schedule-aware tensor distribution module | Gautham Chinya, Huichu Liu, Arnab Raha, Debabrata Mohapatra, Cormac Brick | 2025-04-29 |
| 11907827 | Schedule-aware tensor distribution module | Gautham Chinya, Huichu Liu, Arnab Raha, Debabrata Mohapatra, Cormac Brick | 2024-02-20 |
| 11714998 | Accelerating neural networks with low precision-based multiplication and exploiting sparsity in higher order bits | Avishaii Abuhatzera, Om Ji Omer, Ritwika Chowdhury | 2023-08-01 |
| 11347828 | Methods, apparatus, articles of manufacture to perform accelerated matrix multiplication | Biji George, Om Ji Omer, Dipan Kumar Mandal, Cormac Brick, Sreenivas Subramoney +1 more | 2022-05-31 |
| 9830954 | Method and system for dynamic power management of memories | Hee Jun Park | 2017-11-28 |
| 9372768 | Debug interface | Jeremy Conner, Sabar Souag, Karunakara Kotary, Victor Ruybalid, Noel Eck +2 more | 2016-06-21 |
| 9189439 | Interface logic for a multi-core system-on-a-chip (SoC) | Ramana Rachakonda, Mahesh K. Reddy, Lori R. Borger, Chee Hak Teh, Pawitter P. Bhatia +1 more | 2015-11-17 |
| 9189302 | Technique for monitoring activity within an integrated circuit | — | 2015-11-17 |
| 8656411 | Technique for monitoring activity within an integrated circuit | — | 2014-02-18 |
| 8650629 | Interface logic for a multi-core system-on-a-chip (SoC) | Ramana Rachakonda, Mahesh K. Reddy, Lori R. Borger, Chee Hak Teh, Pawitter P. Bhatia +1 more | 2014-02-11 |
| 8412855 | Write combining protocol between processors and chipsets | Kenneth C. Creta, Aaron T. Spink, Sridhar Muthrasanallur, Jasmin Ajanovic | 2013-04-02 |
| 8392728 | Reducing idle leakage power in an IC | Belliappa Kuttanna, Rajesh Patel, Ashish V. Choubal, Terry Fletcher, Steven S. Varnum +1 more | 2013-03-05 |
| 8312309 | Technique for promoting determinism among multiple clock domains | Eric L. Hendrickson, Sanjoy K. Mondal, Larry Edward Thatcher, William Hodges, Sankaran M. Menon | 2012-11-13 |
| 8289850 | Interconnect bandwidth throttler | Ramana Rachakonda, Belliappa Kuttanna, Rajesh Patel | 2012-10-16 |
| 8050177 | Interconnect bandwidth throttler | Ramana Rachakonda, Belliappa Kuttanna, Rajesh Patel | 2011-11-01 |
| 7877619 | Power mode control method and circuitry | Ramana Rachakonda, Blaise Fanning, Anil K. Sabbavarapu, Belliappa Kuttanna, Rajesh Patel +3 more | 2011-01-25 |
| 7707350 | Bus interconnect switching mechanism | Michael Altenburg, Binta M. Patel, David K. Dean | 2010-04-27 |
| 7676603 | Write combining protocol between processors and chipsets | Kenneth C. Creta, Aaron T. Spink, Sridhar Muthrasanallur, Jasmin Ajanovic | 2010-03-09 |
| 7360103 | P-state feedback to operating system with hardware coordination | Bernard Lint, Alon Naveh, Shivnandan Kaushik, Jeffrey R. Wilcox, Ping Sager +2 more | 2008-04-15 |
| 7315952 | Power state coordination between devices sharing power-managed resources | Jeffrey R. Wilcox, Shivnandan Kaushik, Stephen H. Gunther, Devadatta V. Bodas, Siva Ramakrishnan +1 more | 2008-01-01 |
| 7284118 | Method and apparatus for synchronizing load operations | Debbie Marr | 2007-10-16 |
| 7272741 | Hardware coordination of power management activities | Jeffrey R. Wilcox, Shivnandan Kaushik, Stephen H. Gunther, Devadatta V. Bodas, Siva Ramakrishnan +2 more | 2007-09-18 |
| 7249245 | Globally observing load operations prior to fence instruction and post-serialization modes | Debbie Marr | 2007-07-24 |
| 6978357 | Method and apparatus for performing cache segment flush and cache segment invalidation operations | Shreekant S. Thakkar, Thomas R. Huff, Vladimir Pentkovski, Hsien-Cheng E. Hsieh | 2005-12-20 |
| 6862679 | Synchronization of load operations using load fence instruction in pre-serialization/post-serialization mode | Debbie Marr | 2005-03-01 |