Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
LH

Lance Hacking — 29 Patents

Intel: 28 patents #1,370 of 30,777Top 5%
Spanish Fork, UT: #8 of 197 inventorsTop 5%
Utah: #510 of 19,430 inventorsTop 3%
Overall (All Time): #127,851 of 4,157,543Top 4%
29 Patents All Time
Lance Hacking has been granted 29 US patents while listed as an inventor at Intel. The first was granted in 1999 and the most recent in April 2025. Lance Hacking ranks #127,851 of 4,157,543 US inventors in our database (top 3.1%). Patent records list Lance Hacking in Spanish Fork, UT, US.

Issued Patents All Time

Showing 1–25 of 29 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12288153 Schedule-aware tensor distribution module Gautham Chinya, Huichu Liu, Arnab Raha, Debabrata Mohapatra, Cormac Brick 2025-04-29
11907827 Schedule-aware tensor distribution module Gautham Chinya, Huichu Liu, Arnab Raha, Debabrata Mohapatra, Cormac Brick 2024-02-20 $26,968,000
11714998 Accelerating neural networks with low precision-based multiplication and exploiting sparsity in higher order bits Avishaii Abuhatzera, Om Ji Omer, Ritwika Chowdhury 2023-08-01 $26,467,000
11347828 Methods, apparatus, articles of manufacture to perform accelerated matrix multiplication Biji George, Om Ji Omer, Dipan Kumar Mandal, Cormac Brick, Sreenivas Subramoney +1 more 2022-05-31 $16,893,000
9830954 Method and system for dynamic power management of memories Hee Jun Park 2017-11-28 $12,678,000
9372768 Debug interface Jeremy Conner, Sabar Souag, Karunakara Kotary, Victor Ruybalid, Noel Eck +2 more 2016-06-21 $13,200,000
9189439 Interface logic for a multi-core system-on-a-chip (SoC) Ramana Rachakonda, Mahesh K. Reddy, Lori R. Borger, Chee Hak Teh, Pawitter P. Bhatia +1 more 2015-11-17 $15,457,000
9189302 Technique for monitoring activity within an integrated circuit 2015-11-17 $15,457,000
8656411 Technique for monitoring activity within an integrated circuit 2014-02-18 $23,747,000
8650629 Interface logic for a multi-core system-on-a-chip (SoC) Ramana Rachakonda, Mahesh K. Reddy, Lori R. Borger, Chee Hak Teh, Pawitter P. Bhatia +1 more 2014-02-11 $23,363,000
8412855 Write combining protocol between processors and chipsets Kenneth C. Creta, Aaron T. Spink, Sridhar Muthrasanallur, Jasmin Ajanovic 2013-04-02 $10,070,000
8392728 Reducing idle leakage power in an IC Belliappa Kuttanna, Rajesh Patel, Ashish V. Choubal, Terry Fletcher, Steven S. Varnum +1 more 2013-03-05 $12,770,000
8312309 Technique for promoting determinism among multiple clock domains Eric L. Hendrickson, Sanjoy K. Mondal, Larry Edward Thatcher, William Hodges, Sankaran M. Menon 2012-11-13 $15,347,000
8289850 Interconnect bandwidth throttler Ramana Rachakonda, Belliappa Kuttanna, Rajesh Patel 2012-10-16 $11,593,000
8050177 Interconnect bandwidth throttler Ramana Rachakonda, Belliappa Kuttanna, Rajesh Patel 2011-11-01 $63,216,000
7877619 Power mode control method and circuitry Ramana Rachakonda, Blaise Fanning, Anil K. Sabbavarapu, Belliappa Kuttanna, Rajesh Patel +3 more 2011-01-25
7707350 Bus interconnect switching mechanism Michael Altenburg, Binta M. Patel, David K. Dean 2010-04-27 $12,857,000
7676603 Write combining protocol between processors and chipsets Kenneth C. Creta, Aaron T. Spink, Sridhar Muthrasanallur, Jasmin Ajanovic 2010-03-09 $23,050,000
7360103 P-state feedback to operating system with hardware coordination Bernard Lint, Alon Naveh, Shivnandan Kaushik, Jeffrey R. Wilcox, Ping Sager +2 more 2008-04-15 $20,104,000
7315952 Power state coordination between devices sharing power-managed resources Jeffrey R. Wilcox, Shivnandan Kaushik, Stephen H. Gunther, Devadatta V. Bodas, Siva Ramakrishnan +1 more 2008-01-01
7284118 Method and apparatus for synchronizing load operations Debbie Marr 2007-10-16 $25,589,000
7272741 Hardware coordination of power management activities Jeffrey R. Wilcox, Shivnandan Kaushik, Stephen H. Gunther, Devadatta V. Bodas, Siva Ramakrishnan +2 more 2007-09-18 $14,997,000
7249245 Globally observing load operations prior to fence instruction and post-serialization modes Debbie Marr 2007-07-24 $22,724,000
6978357 Method and apparatus for performing cache segment flush and cache segment invalidation operations Shreekant S. Thakkar, Thomas R. Huff, Vladimir Pentkovski, Hsien-Cheng E. Hsieh 2005-12-20 $37,307,000
6862679 Synchronization of load operations using load fence instruction in pre-serialization/post-serialization mode Debbie Marr 2005-03-01 $28,008,000