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USPTO Patent Rankings Data through Dec 31, 2025
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Alon Naveh — 100 Patents

Intel: 90 patents #250 of 30,777Top 1%
Qualcomm: 10 patents #2,065 of 12,104Top 20%
Corte Madera, CA: #2 of 143 inventorsTop 2%
California: #2,278 of 386,348 inventorsTop 1%
Overall (All Time): #14,510 of 4,157,543Top 1%
100 Patents All Time
Alon Naveh has been granted 100 US patents while listed as an inventor at Intel. The first was granted in 2005 and the most recent in November 2025. Alon Naveh ranks #14,510 of 4,157,543 US inventors in our database (top 0.35%). Patent records list Alon Naveh in Corte Madera, CA, US.

Issued Patents All Time

Showing 1–25 of 100 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12475335 Broadcasting power limiting management responses in a processor-based system in an integrated circuit (IC) chip Sagar Koorapati, Vinod Chamarty 2025-11-18
12468375 Hierarchical power estimation and throttling in a processor-based system in an integrated circuit (IC) chip Vinod Chamarty, Sagar Koorapati 2025-11-11
12436590 Time synchronization of collecting and reporting power events between hierarchical power throttling circuits in a hierarchical power management system Vinod Chamarty, Sagar Koorapati, Sreeram Jayadev 2025-10-07
12411518 Throttle control circuits for throttling activity in processing segment circuits in an integrated circuit (IC) chip and related methods Sagar Koorapati 2025-09-09
12411748 Converting telemetry values into common data formats in a processor-based system in an integrated circuit (IC) chip Sagar Koorapati, Pradeep Kanapathipillai 2025-09-09
12379762 Dynamic power management for SoC-based electronic devices Anubhav Mishra, Manu Gulati 2025-08-05
12366905 Integrated circuits (IC) chips including throttle request accumulate circuits for controlling power consumed in processing circuits and related methods Sagar Koorapati, Vinod Chamarty, Gaurav Sanjeev Kirtane, Pushkin Raj Pari, Nitin Makhija 2025-07-22
12287688 Integrated circuits (IC) chips including throttle request accumulate circuits for controlling power consumed in processing circuits and related methods Sagar Koorapati, Vinod Chamarty, Gaurav Sanjeev Kirtane, Pushkin Raj Pari, Nitin Makhija 2025-04-29
12228988 Merging of power events related to estimated power consumption of different devices in a hierarchical power management system in an integrated circuit (IC) chip to perform power throttling Sagar Koorapati 2025-02-18
11733757 Hierarchical power management architecture for SoC-based electronic devices Anubhav Mishra, Manu Gulati 2023-08-22 $9,574,000
11687139 Multi-level CPU high current protection Efraim Rotem, Nir Rosenzweig, Doron Rajwan, Eliezer Weissmann 2023-06-27 $18,721,000
11467740 Method, apparatus, and system for energy efficiency and energy conservation including autonomous hardware-based deep power down in devices Inder M. Sodhi, Doron Rajwan, Ryan D. Wells, Eric C. Samson 2022-10-11 $16,542,000
11307628 Multi-level CPU high current protection Efraim Rotem, Nir Rosenzweig, Doron Rajwan, Eliezer Weissmann 2022-04-19 $22,207,000
11287871 Operating point management in multi-core architectures Efraim Rotem, Oren Lamdan 2022-03-29 $28,068,000
11243768 Mechanism for saving and retrieving micro-architecture context Efraim Rotem, Eliezer Weissmann, Boris Ginzburg, Nadav Shulman, Ronny Ronen 2022-02-08 $27,206,000
10613614 Dynamically controlling cache size to maximize energy efficiency Avinash N. Ananthakrishnan, Efraim Rotem, Eliezer Weissmann, Doron Rajwan, Nadav Shulman +1 more 2020-04-07 $35,530,000
10564699 Dynamically controlling cache size to maximize energy efficiency Avinash N. Ananthakrishnan, Efraim Rotem, Eliezer Weissmann, Doron Rajwan, Nadav Shulman +1 more 2020-02-18 $23,634,000
10509576 Method, apparatus, and system for energy efficiency and energy conservation including autonomous hardware-based deep power down in devices Inder M. Sodhi, Doron Rajwan, Ryan D. Wells, Eric C. Samson 2019-12-17 $31,829,000
10503517 Method for booting a heterogeneous system and presenting a symmetric core view Eliezer Weissmann, Rinat Rappoport, Michael Mishaeli, Hisham Shafi, Oron Lenz +19 more 2019-12-10 $22,400,000
10474218 Dynamically controlling cache size to maximize energy efficiency Avinash N. Ananthakrishnan, Efraim Rotem, Eliezer Weissmann, Doron Rajwan, Nadav Shulman +1 more 2019-11-12 $21,873,000
10379596 Providing an interface for demotion control information in a processor Eliezer Weissmann, Nir Rosenzweig, Efraim Rotem, Yoav Ben-Raphael 2019-08-13 $24,877,000
10372197 User level control of power management policies Krishnakanth V. Sistla, Jeremy J. Shrall, Stephen H. Gunther, Efraim Rotem, Eliezer Weissmann +7 more 2019-08-06 $15,127,000
10191742 Mechanism for saving and retrieving micro-architecture context Efraim Rotem, Eliezer Weissmann, Boris Ginzburg, Nadav Shulman, Ronny Ronen 2019-01-29 $23,219,000
10185566 Migrating tasks between asymmetric computing elements of a multi-core processor Yuval Yosef, Eliezer Weissmann, Anil Aggarwal, Efraim Rotem, Avi Mendelson +7 more 2019-01-22 $27,645,000
10162687 Selective migration of workloads between heterogeneous compute elements based on evaluation of migration performance benefit and available energy and thermal budgets Eugene Gorbatov, Inder M. Sodhi, Ganapati Srinivasa, Eliezer Weissmann, Guarav Khanna +6 more 2018-12-25