AA

Avinash N. Ananthakrishnan

IN Intel: 76 patents #337 of 30,777Top 2%
Overall (All Time): #24,667 of 4,157,543Top 1%
76
Patents All Time

Issued Patents All Time

Showing 25 most recent of 76 patents

Patent #TitleCo-InventorsDate
12366910 Multi-level loops for computer processor control Doron Rajwan, Efraim Rotem, Eliezer Weissmann, Dorit Shapira 2025-07-22
12210395 Techniques to enable communication between a processor and voltage regulator Anupama Suryanarayanan, Chinmay Ashok, Jeremy J. Shrall 2025-01-28
12182618 System, apparatus and method for providing hardware state feedback to an operating system in a heterogeneous processor Praveen Gupta, Eugene Gorbatov, Stephen H. Gunther 2024-12-31
12045114 Throttling of components using priority ordering Jeremy J. Shrall 2024-07-23
11782492 Techniques to enable communication between a processor and voltage regulator Anupama Suryanarayanan, Chinmay Ashok, Jeremy J. Shrall 2023-10-10
11775036 Enhanced power management for support of priority system events Muhammad Abozaed, Eugene Gorbatov, Gaurav Khanna 2023-10-03
11698812 System, apparatus and method for providing hardware state feedback to an operating system in a heterogeneous processor Praveen Gupta, Eugene Gorbatov, Stephen H. Gunther 2023-07-11
11481013 Multi-level loops for computer processor control Doron Rajwan, Efraim Rotem, Eliezer Weissmann, Dorit Shapira 2022-10-25
11442529 System, apparatus and method for dynamically controlling current consumption of processing circuits of a processor Ameya Ambardekar, Ankush Varma, Nimrod Angel, Nir Rosenzweig, Arik Gihon +3 more 2022-09-13
11402887 Techniques to enable communication between a processor and voltage regulator Anupama Suryanarayanan, Chinmay Ashok, Jeremy J. Shrall 2022-08-02
11392187 Enhanced power management for support of priority system events Muhammad Abozaed, Eugene Gorbatov, Gaurav Khanna 2022-07-19
11269396 Per-core operating voltage and/or operating frequency determination based on effective core utilization Stephen H. Gunther, Amr Muhammad Lotfy El-Sayed, Akshay Parnami 2022-03-08
11119555 Processor to pre-empt voltage ramps for exit latency reductions Jeremy J. Shrall, Anupama Suryanarayanan, Ameya Ambardekar, Craig Topper, Eric Heit +1 more 2021-09-14
11099628 Throttling of components using priority ordering Jeremy J. Shrall 2021-08-24
10976801 System, apparatus and method for power budget distribution for a plurality of virtual machines to execute on a processor Nikhil Gupta 2021-04-13
10761580 Techniques to enable communication between a processor and voltage regulator Anupama Suryanarayanan, Chinmay Ashok, Jeremy J. Shrall 2020-09-01
10705588 Enabling a non-core domain to control memory bandwidth in a processor Inder M. Sodhi, Efraim Rotem, Doron Rajwan, Eliezer Weissmann, Ryan D. Wells 2020-07-07
10678319 Multi-level loops for computer processor control Doron Rajwan, Efraim Rotem, Eliezer Weissmann, Dorit Shapira 2020-06-09
10620969 System, apparatus and method for providing hardware feedback information in a processor Vedvyas Shanbhogue, Eugene Gorbatov, Russell J. Fenger, Ashok Raj, Kameswar Subramaniam 2020-04-14
10613614 Dynamically controlling cache size to maximize energy efficiency Efraim Rotem, Eliezer Weissmann, Doron Rajwan, Nadav Shulman, Alon Naveh +1 more 2020-04-07
10606338 Energy-aware power sharing control Sudheer Nair, James G. Hermerding, II 2020-03-31
10564699 Dynamically controlling cache size to maximize energy efficiency Efraim Rotem, Eliezer Weissmann, Doron Rajwan, Nadav Shulman, Alon Naveh +1 more 2020-02-18
10545793 Thread scheduling using processing engine information Vijay Dhanraj, Russell J. Fenger, Vivek Garg, Eugene Gorbatov, Stephen H. Gunther +6 more 2020-01-28
10503226 Enhanced power management for support of priority system events Muhammad Abozaed, Eugene Gorbatov, Gaurav Khanna 2019-12-10
10474218 Dynamically controlling cache size to maximize energy efficiency Efraim Rotem, Eliezer Weissmann, Doron Rajwan, Nadav Shulman, Alon Naveh +1 more 2019-11-12