Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10664284 | Apparatus and method for a hybrid latency-throughput processor | Oren Ben-Kiki, Ilan Pardo, Dror Markovich | 2020-05-26 |
| 10346195 | Apparatus and method for invocation of a multi threaded accelerator | Oren Ben-Kiki, Ilan Pardo, Eliezer Weissmann, Robert Valentine | 2019-07-09 |
| 10255077 | Apparatus and method for a hybrid latency-throughput processor | Oren Ben-Kiki, Ilan Pardo, Dror Markovich | 2019-04-09 |
| 10185566 | Migrating tasks between asymmetric computing elements of a multi-core processor | Alon Naveh, Eliezer Weissmann, Anil Aggarwal, Efraim Rotem, Avi Mendelson +7 more | 2019-01-22 |
| 10140129 | Processing core having shared front end unit | Ilan Pardo, Dror Markovich, Oren Ben-Kiki | 2018-11-27 |
| 10101999 | Memory address collision detection of ordered parallel threads with bloom filters | Enrique de Lucas, Pedro Marcuello, Oren Ben-Kiki, Ilan Pardo | 2018-10-16 |
| 10095521 | Apparatus and method for low-latency invocation of accelerators | Oren Ben-Kiki, Ilan Pardo, Robert Valentine, Eliezer Weissmann, Dror Markovich | 2018-10-09 |
| 10089113 | Apparatus and method for low-latency invocation of accelerators | Oren Ben-Kiki, Ilan Pardo, Robert Valentine, Eliezer Weissmann, Dror Markovich | 2018-10-02 |
| 10083037 | Apparatus and method for low-latency invocation of accelerators | Oren Ben-Kiki, Ilan Pardo, Robert Valentine, Eliezer Weissmann, Dror Markovich | 2018-09-25 |
| 9720730 | Providing an asymmetric multicore processor system transparently to an operating system | Boris Ginzburg, Ilya Osadchiy, Ronny Ronen, Eliezer Weissmann, Michael Mishaeli +13 more | 2017-08-01 |
| 9588771 | Instruction set architecture-based inter-sequencer communications with a heterogeneous resource | Hong Wang, John Shen, Hong Jiang, Richard Hankins, Per Hammarlund +8 more | 2017-03-07 |
| 9542193 | Memory address collision detection of ordered parallel threads with bloom filters | Enrique de Lucas, Pedro Marcuello, Oren Ben-Kiki, Ilan Pardo | 2017-01-10 |
| 9459874 | Instruction set architecture-based inter-sequencer communications with a heterogeneous resource | Hong Wang, John Shen, Hong Jiang, Richard Hankins, Per Hammarlund +8 more | 2016-10-04 |
| 9417873 | Apparatus and method for a hybrid latency-throughput processor | Oren Ben-Kiki, Ilan Pardo, Dror Markovich | 2016-08-16 |
| 9361116 | Apparatus and method for low-latency invocation of accelerators | Oren Ben-Kiki, Ilan Pardo, Robert Valentine, Eliezer Weissmann, Dror Markovich | 2016-06-07 |
| 9032223 | Techniques to manage operational parameters for a processor | Efraim Rotem, Eric Distefano, Jim Hermerding, Ronny Korner | 2015-05-12 |
| 8914618 | Instruction set architecture-based inter-sequencer communications with a heterogeneous resource | Hong Wang, John Shen, Hong Jiang, Richard Hankins, Per Hammarlund +8 more | 2014-12-16 |
| 8166320 | Power aware software pipelining for hardware accelerators | Ron Gabor, Hong Jiang, Alon Naveh, Doron Rajwan, James Varga +1 more | 2012-04-24 |
| 7725745 | Power aware software pipelining for hardware accelerators | Ron Gabor, Hong Jiang, Alon Naveh, Doron Rajwan, James Varga +1 more | 2010-05-25 |