Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10157063 | Instruction and logic for optimization level aware branch prediction | Polychronis Xekalakis, Alejandro Vicente Martinez, Christos E. Kotselidis, Grigorios Magklis, Fernando Latorre +13 more | 2018-12-18 |
| 10101999 | Memory address collision detection of ordered parallel threads with bloom filters | Enrique de Lucas, Oren Ben-Kiki, Ilan Pardo, Yuval Yosef | 2018-10-16 |
| 10013326 | Propagating a prefetching profile bit from a prefetch queue to a data cache to indicate that a line was prefetched in response to an instruction within a code region | Raul Martinez, Enric Gibert Codina, Pedro Lopez, Marti Torrents Lapuerta, Polychronis Xekalakis +14 more | 2018-07-03 |
| 9940686 | Exploiting frame to frame coherency in a sort-middle architecture | Juan Fernandez, Javier Carretero Casado, Tomas G. Akenine-Moller | 2018-04-10 |
| 9922393 | Exploiting frame to frame coherency in a sort-middle architecture | Juan Fernandez, Javier Carretero Casado, Tomas G. Akenine-Moller | 2018-03-20 |
| 9904977 | Exploiting frame to frame coherency in a sort-middle architecture | Juan Fernandez, Javier Carretero Casado, Tomas G. Akenine-Moller | 2018-02-27 |
| 9811341 | Managed instruction cache prefetching | Kyriakos A. Stavrou, Enric Gibert Codina, Josep M. Codina, Crispin Gomez Requena, Antonio Gonzalez +13 more | 2017-11-07 |
| D785510 | Pram | — | 2017-05-02 |
| 9542193 | Memory address collision detection of ordered parallel threads with bloom filters | Enrique de Lucas, Oren Ben-Kiki, Ilan Pardo, Yuval Yosef | 2017-01-10 |
| 9374542 | Image signal processor with a block checking circuit | Kyriakos A. Stavrou, Grigorios Magklis, Javier Carretero Casado, Juan Fernandez, Carlos Madriles +2 more | 2016-06-21 |
| 8813057 | Branch pruning in architectures with speculation support | Carlos García Quiñones, Jesus Sanchez, Carlos Madriles, Antonio Gonzalez | 2014-08-19 |
| 8719806 | Speculative multi-threading for instruction prefetch and/or trace pre-build | Hong Wang, Tor M. Aamodt, Jared W. Stark, IV, John Shen, Antonio Gonzalez +4 more | 2014-05-06 |
| 8612698 | Replacement policy for hot code detection | Pedro Lopez, F. Jesus Sanchez, Josep M. Codina, Enric Gibert, Fernando Latorre +2 more | 2013-12-17 |
| 8185700 | Enabling speculative state information in a cache coherency protocol | Carlos Madriles Gimeno, Carlos García Quiñones, Jesus Sanchez, Fernando Latorre, Antonio Gonzalez | 2012-05-22 |
| 8166282 | Multi-version register file for multithreading processors with live-in precomputation | Carlos Madriles, Peter Rundberg, Jesus Sanchez, Carlos Garcia, Antonio Gonzalez | 2012-04-24 |
| 7814469 | Speculative multi-threading for instruction prefetch and/or trace pre-build | Hong Wang, Tor M. Aamodt, Jared W. Stark, IV, John Shen, Antonio Gonzalez +4 more | 2010-10-12 |
| 7458065 | Selection of spawning pairs for a speculative multithreaded processor | Jesus Sanchez, Carlos Garcia, Carlos Madriles, Peter Rundberg, Antonio Gonzalez | 2008-11-25 |