Issued Patents All Time
Showing 25 most recent of 39 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11977884 | Replicate elements instruction | Jacob Eapen, Mbou Eyole | 2024-05-07 |
| 11947962 | Replicate partition instruction | Jacob Eapen, Mbou Eyole | 2024-04-02 |
| 11775297 | Transaction nesting depth testing instruction | Matthew James Horsnell, Stephan Diestelhorst | 2023-10-03 |
| 11663034 | Permitting unaborted processing of transaction after exception mask update instruction | Matthew James Horsnell, Richard Roy Grisenthwaite, Stephan Diestelhorst | 2023-05-30 |
| 11615032 | Address translation data invalidation | Matthew James Horsnell, Richard Roy Grisenthwaite | 2023-03-28 |
| 11579873 | Handling load-exclusive instructions in apparatus having support for transactional memory | Matthew James Horsnell, Richard Roy Grisenthwaite, Nathan Yong Seng Chong | 2023-02-14 |
| 11513796 | Multiply-accumulation in a data processing apparatus | David Hennah Mansell | 2022-11-29 |
| 11481290 | Exception handling in transactions | Matthew James Horsnell, Stephan Diestelhorst | 2022-10-25 |
| 11422807 | Testing bit values inside vector elements | Nigel John Stephens | 2022-08-23 |
| 11422808 | Transactional compare-and-discard instruction | Matthew James Horsnell, Stephan Diestelhorst | 2022-08-23 |
| 11327752 | Element by vector operations in a data processing apparatus | Nigel John Stephens, Jacob Eapen, Mbou Eyole, David Hennah Mansell | 2022-05-10 |
| 11314514 | Vector length querying instruction | Nigel John Stephens, Alejandro Martinez Vicente, Nathanael Premillieu | 2022-04-26 |
| 11106465 | Vector add-with-carry instruction | Mbou Eyole, Nigel John Stephens, Neil Burgess | 2021-08-31 |
| 10824350 | Handling contingent and non-contingent memory access program instructions making use of disable flag | Nigel John Stephens | 2020-11-03 |
| 10430192 | Vector processing using loops of dynamic vector length | Nigel John Stephens, Alejandro Martinez Vicente, Nathanael Premillieu, Mbou Eyole | 2019-10-01 |
| 10157063 | Instruction and logic for optimization level aware branch prediction | Polychronis Xekalakis, Pedro Marcuello, Alejandro Vicente Martinez, Christos E. Kotselidis, Fernando Latorre +13 more | 2018-12-18 |
| 10061587 | Instruction and logic for bulk register reclamation | David Keppel, Denis M. Khartikov, Fernando Latorre, Marc Lupon, Naveen Neelakantam +2 more | 2018-08-28 |
| 10013326 | Propagating a prefetching profile bit from a prefetch queue to a data cache to indicate that a line was prefetched in response to an instruction within a code region | Raul Martinez, Enric Gibert Codina, Pedro Lopez, Marti Torrents Lapuerta, Polychronis Xekalakis +14 more | 2018-07-03 |
| 9811341 | Managed instruction cache prefetching | Kyriakos A. Stavrou, Enric Gibert Codina, Josep M. Codina, Crispin Gomez Requena, Antonio Gonzalez +13 more | 2017-11-07 |
| 9778909 | Double rounded combined floating-point multiply and add | Sridhar Samudrala, Marc Lupon, David R. Ditzel | 2017-10-03 |
| 9477441 | Double rounded combined floating-point multiply and add | Sridhar Samudrala, Marc Lupon, David R. Ditzel | 2016-10-25 |
| 9389871 | Combined floating point multiplier adder with intermediate rounding logic | Marc Lupon, Sridhar Samudrala, Raul Martinez, Kyriakos A. Stavrou, Enric Gibert Codina | 2016-07-12 |
| 9374542 | Image signal processor with a block checking circuit | Kyriakos A. Stavrou, Pedro Marcuello, Javier Carretero Casado, Juan Fernandez, Carlos Madriles +2 more | 2016-06-21 |
| 9329848 | Mechanism for facilitating dynamic and efficient fusion of computing instructions in software programs | Marc Lupon, Raul Martinez, Enric Gibert Codina, Kyriakos A. Stavrou, Sridhar Samudrala | 2016-05-03 |
| 9213523 | Double rounded combined floating-point multiply and add | Sridhar Samudrala, Marc Lupon, David R. Ditzel | 2015-12-15 |