MH

Matthew James Horsnell

NV NVIDIA: 31 patents #157 of 7,811Top 3%
Overall (All Time): #115,054 of 4,157,543Top 3%
31
Patents All Time

Issued Patents All Time

Showing 25 most recent of 31 patents

Patent #TitleCo-InventorsDate
12373350 Cache-line retention hint information for conditional write instruction Andreas Lars Sandberg, Thomas Philip Speier, Robin Alexander Emery, Eric Ola Harald Liljedahl 2025-07-29
12346693 Monitor exclusive instruction 2025-07-01
12265603 Electronic authentication system, device and process Daren Croxford, Roberto Lopez Mendez, Mbou Eyole 2025-04-01
12236091 Monitoring memory locations to identify whether data stored at the memory locations has been modified 2025-02-25
12216589 Draining operation for draining dirty cache lines to persistent memory Wei Wang 2025-02-04
11803627 Authentication system, device and process Mbou Eyole 2023-10-31
11797415 Apparatus and method for monitoring events in a data processing system Timothy Hayes, Giacomo Gabrielli 2023-10-24
11775297 Transaction nesting depth testing instruction Grigorios Magklis, Stephan Diestelhorst 2023-10-03
11663034 Permitting unaborted processing of transaction after exception mask update instruction Grigorios Magklis, Richard Roy Grisenthwaite, Stephan Diestelhorst 2023-05-30
11615032 Address translation data invalidation Grigorios Magklis, Richard Roy Grisenthwaite 2023-03-28
11579873 Handling load-exclusive instructions in apparatus having support for transactional memory Grigorios Magklis, Richard Roy Grisenthwaite, Nathan Yong Seng Chong 2023-02-14
11481290 Exception handling in transactions Grigorios Magklis, Stephan Diestelhorst 2022-10-25
11422808 Transactional compare-and-discard instruction Grigorios Magklis, Stephan Diestelhorst 2022-08-23
11379233 Apparatus and data processing method for transactional memory Richard Roy Grisenthwaite 2022-07-05
11347539 Checking lock variables for transactions in a system with transactional memory support Stephan Diestelhorst 2022-05-31
11086626 Circuitry and methods Roko Grubisic, Giacomo Gabrielli, Syed Ali Mustafa Zaidi 2021-08-10
10922084 Handling of inter-element address hazards for vector instructions Mbou Eyole 2021-02-16
10908944 Apparatus with shared transactional processing resource, and data processing method Stephan Diestelhorst, Guy Larri 2021-02-02
10866805 Speculation barrier instruction Richard Roy Grisenthwaite, Giacomo Gabrielli 2020-12-15
10838730 Saving and restoring branch prediction state Ilias Vougioukas, Andreas Lars Sandberg, Stephan Diestelhorst 2020-11-17
10810039 Monitoring utilization of transactional processing resource Stephan Diestelhorst 2020-10-20
10678595 Dynamic saving of registers in transactions Stephan Diestelhorst 2020-06-09
10572299 Switching between thread mode and transaction mode for a set of registers Stephan Diestelhorst, Guy Larri 2020-02-25
10523186 Vulnerability determination in circuits Balaji Venu, Reiley Jeyapaul, Xabier Iturbe, David Michael Gilday 2019-12-31
10394557 Debugging data processing transactions Stephan Diestelhorst, Michael John Williams, Richard Roy Grisenthwaite 2019-08-27