| 12231339 |
Extension of openvswitch megaflow offloads to hardware to address hardware pipeline limitations |
Namrata Limaye, Venkata Suresh Kumar Paruchuri, Kiran Patil |
2025-02-18 |
|
| 12170624 |
Technologies that provide policy enforcement for resource access |
Anjali Singhai Jain, Daniel Daly, Linden Cornett, Phani Burra, Brett Creeley |
2024-12-17 |
$33,648,000 |
| 12086594 |
Vector friendly instruction format and execution thereof |
Robert Valentine, Jesus Corbal San Adrian, Roger Espasa Sans, Robert Dale Cavin, Bret L. Toll +14 more |
2024-09-10 |
$16,964,000 |
| 11740904 |
Vector friendly instruction format and execution thereof |
Robert Valentine, Jesus Corbal San Adrian, Roger Espasa Sans, Robert Dale Cavin, Bret L. Toll +14 more |
2023-08-29 |
$19,273,000 |
| 11210096 |
Vector friendly instruction format and execution thereof |
Robert Valentine, Jesus Corbal San Adrian, Roger Espasa Sans, Robert Dale Cavin, Bret L. Toll +14 more |
2021-12-28 |
$27,770,000 |
| 10795680 |
Vector friendly instruction format and execution thereof |
Robert Valentine, Jesus Corbal San Adrian, Roger Espasa Sans, Robert Dale Cavin, Bret L. Toll +14 more |
2020-10-06 |
$29,609,000 |
| 10135687 |
Virtual group policy based filtering within an overlay network |
Vivek Kashyap, David Stevens |
2018-11-20 |
|
| 10037205 |
Instruction and logic to provide vector blend and permute functionality |
Robert Valentine, Bret L. Toll, Jesus Corbal, Jeffrey G. Wiedemeier |
2018-07-31 |
$36,087,000 |
| 9778909 |
Double rounded combined floating-point multiply and add |
Grigorios Magklis, Marc Lupon, David R. Ditzel |
2017-10-03 |
$11,313,000 |
| 9513917 |
Vector friendly instruction format and execution thereof |
Robert Valentine, Jesus Corbal San Adrian, Roger Espasa Sans, Robert Dale Cavin, Bret L. Toll +14 more |
2016-12-06 |
$8,381,000 |
| 9477441 |
Double rounded combined floating-point multiply and add |
Grigorios Magklis, Marc Lupon, David R. Ditzel |
2016-10-25 |
$11,658,000 |
| 9389871 |
Combined floating point multiplier adder with intermediate rounding logic |
Marc Lupon, Grigorios Magklis, Raul Martinez, Kyriakos A. Stavrou, Enric Gibert Codina |
2016-07-12 |
$10,128,000 |
| 9329848 |
Mechanism for facilitating dynamic and efficient fusion of computing instructions in software programs |
Marc Lupon, Raul Martinez, Enric Gibert Codina, Kyriakos A. Stavrou, Grigorios Magklis |
2016-05-03 |
$11,131,000 |
| 9213523 |
Double rounded combined floating-point multiply and add |
Grigorios Magklis, Marc Lupon, David R. Ditzel |
2015-12-15 |
$18,227,000 |
| 9141386 |
Vector logical reduction operation implemented using swizzling on a semiconductor chip |
Jeff Wiedemeier, Roger Golliver |
2015-09-22 |
$9,820,000 |
| 9092213 |
Functional unit for vector leading zeroes, vector trailing zeroes, vector operand 1s count and vector parity calculation |
Jeff Wiedemeier, Roger Golliver, Eric W. Mahurin |
2015-07-28 |
$15,934,000 |
| 8667042 |
Functional unit for vector integer multiply add instruction |
Jeff Wiedemeier, Roger Golliver |
2014-03-04 |
$18,335,000 |
| 7127483 |
Method and system of a microprocessor subtraction-division floating point divider |
Andrew J. Beaumont-Smith |
2006-10-24 |
$29,050,000 |
| 6779012 |
Computer method and apparatus for division and square root operations using signed digit |
Mark D. Matson, Robert J. Dupcak, Jonathan Krause |
2004-08-17 |
$8,169,000 |
| 6732135 |
Method and apparatus for accumulating partial quotients in a digital processor |
John D. Clouser, William R. Grundmann |
2004-05-04 |
$12,475,000 |
| 6564239 |
Computer method and apparatus for division and square root operations using signed digit |
Mark D. Matson, Robert J. Dupcak, Jonathan Krause |
2003-05-13 |
$16,526,000 |
| 6366942 |
Method and apparatus for rounding floating point results in a digital processing system |
Roy Badeau, William R. Grundmann, Mark D. Matson |
2002-04-02 |
$13,864,000 |
| 6360241 |
Computer method and apparatus for division and square root operations using signed digit |
Mark D. Matson, Robert J. Dupcak, Jonathan Krause |
2002-03-19 |
$17,590,000 |
| 6144228 |
Generalized push-pull cascode logic technique |
Mark D. Matson, Robert J. Dupcak |
2000-11-07 |
$89,641,000 |
| 5341319 |
Method and apparatus for controlling a rounding operation in a floating point multiplier circuit |
William C. Madden, Vidya Rajagopalan |
1994-08-23 |
$4,671,000 |
