AB

Andrew J. Beaumont-Smith

Apple: 23 patents #1,389 of 18,612Top 8%
HP HP: 1 patents #8,774 of 16,619Top 55%
Overall (All Time): #169,484 of 4,157,543Top 5%
24
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12430224 Debug trace of cache memory requests Sandeep Gupta, Krishna C. Potnuru, Matthias Knoth 2025-09-30
12174785 Coprocessors with bypass optimization, variable grid architecture, and fused vector operations Aditya Kesiraju, Boris S. Alvarez-Heredia, Pradeep Kanapathipillai, Ran A. Chachick 2024-12-24
12135681 Coprocessors with bypass optimization, variable grid architecture, and fused vector operations Aditya Kesiraju, Boris S. Alvarez-Heredia, Ran A. Chachick 2024-11-05
12050918 Coprocessor prefetcher Brandon H. Dwiel, Eric J. Furbish, John D. Pape, Stephen G. Meier, Tyler J. Huberty 2024-07-30
11775301 Coprocessor register renaming using registers associated with an inactive context to store results from an active context Ran A. Chachick, Aditya Kesiraju, Jong-Suk Lee 2023-10-03
11768690 Coprocessor context priority Aditya Kesiraju, Brian P. Lilly, James Vash, Jason M. Kassoff, Krishna C. Potnuru +4 more 2023-09-26
11755333 Coprocessor prefetcher Brandon H. Dwiel, Eric J. Furbish, John D. Pape, Stephen G. Meier, Tyler J. Huberty 2023-09-12
11740993 Debug trace of cache memory requests Sandeep Gupta, Krishna C. Potnuru, Matthias Knoth 2023-08-29
11650825 Coprocessor synchronizing instruction suppression Aditya Kesiraju, Rajdeep L. Bhuyar, Ran A. Chachick 2023-05-16
11429555 Coprocessors with bypass optimization, variable grid architecture, and fused vector operations Aditya Kesiraju, Boris S. Alvarez-Heredia, Srikanth Balasubramanian 2022-08-30
11249766 Coprocessor synchronizing instruction suppression Aditya Kesiraju, Rajdeep L. Bhuyar, Ran A. Chachick 2022-02-15
11210104 Coprocessor context priority Aditya Kesiraju, Brian P. Lilly, James Vash, Jason M. Kassoff, Krishna C. Potnuru +4 more 2021-12-28
10846091 Coprocessor with distributed register Aditya Kesiraju, Deepankar Duggal, Ran A. Chachick 2020-11-24
10831488 Computation engine with extract instructions to minimize memory access Eric Bainville, Jeffry E. Gonion, Ali Sazegari, Gerard R. Williams, III 2020-11-10
9354886 Maintaining the integrity of an execution return address stack Ramesh Gunna, Peter J. Bannon 2016-05-31
9009451 Instruction type issue throttling upon reaching threshold by adjusting counter increment amount for issued cycle and decrement amount for not issued cycle Daniel C. Murray, John H. Mylius, Peter J. Bannon, Toshi Takayanagi, Jung Wook Cho 2015-04-14
8959320 Preventing update training of first predictor with mismatching second predictor for branch instructions with alternating pattern hysteresis Ramesh Gunna 2015-02-17
8566528 Combining write buffer with dynamically adjustable flush metrics Peter J. Bannon, Ramesh Gunna, Wei-Han Lien, Brian P. Lilly, Jaidev P. Patwardhan +2 more 2013-10-22
8555040 Indirect branch target predictor that prevents speculation if mispredict is expected Ramesh Gunna 2013-10-08
8364936 Processor employing split scheduler in which near, low latency operation dependencies are tracked separate from other operation dependencies Honkai Tam, Daniel C. Murray, John H. Mylius, Peter J. Bannon, Pradeep Kanapathipillai 2013-01-29
8352685 Combining write buffer with dynamically adjustable flush metrics Peter J. Bannon, Ramesh Gunna, Wei-Han Lien, Brian P. Lilly, Jaidev P. Patwardhan +2 more 2013-01-08
8285947 Store hit load predictor John H. Mylius 2012-10-09
8255671 Processor employing split scheduler in which near, low latency operation dependencies are tracked separate from other operation dependencies Honkai Tam, Daniel C. Murray, John H. Mylius, Peter J. Bannon, Pradeep Kanapathipillai 2012-08-28
7127483 Method and system of a microprocessor subtraction-division floating point divider Sridhar Samudrala 2006-10-24