JV

James Vash

IN Intel: 24 patents #1,642 of 30,777Top 6%
Apple: 19 patents #1,704 of 18,612Top 10%
Overall (All Time): #69,215 of 4,157,543Top 2%
43
Patents All Time

Issued Patents All Time

Showing 25 most recent of 43 patents

Patent #TitleCo-InventorsDate
12399830 Scalable system on a chip Per Hammarlund, Eran Tamari, Lior Zimet, Sergio Kolor, Sergio V. Tota +6 more 2025-08-26
12332792 Scalable cache coherency protocol Gaurav Garg, Brian P. Lilly, Ramesh Gunna, Steven R. Hutsell, Lital Levy-Rubin +2 more 2025-06-17
12321746 DSB operation with excluded region Jeff Gonion, John H. Kelm, Pradeep Kanapathipillai, Mridul Agarwal, Gideon N. Levinsky +2 more 2025-06-03
12277074 Mechanisms to utilize communication fabric via multi-port architecture Sergio Kolor, Sandeep Gupta 2025-04-15
12253913 Memory error tracking and logging Farid Nemati, Steven R. Hutsell, Derek R. Kumar, Bernard J. Semeria, Era K. Nangia +1 more 2025-03-18
12007895 Scalable system on a chip Per Hammarlund, Eran Tamari, Lior Zimet, Sergio Kolor, Sergio V. Tota +6 more 2024-06-11
11947457 Scalable cache coherency protocol Gaurav Garg, Brian P. Lilly, Ramesh Gunna, Steven R. Hutsell, Lital Levy-Rubin +2 more 2024-04-02
11934265 Memory error tracking and logging Farid Nemati, Steven R. Hutsell, Derek R. Kumar, Bernard J. Semeria, Era K. Nangia +1 more 2024-03-19
11934313 Scalable system on a chip Per Hammarlund, Lior Zimet, Gaurav Garg, Sergio Kolor, Harshavardhan Kaushikkar +2 more 2024-03-19
11868258 Scalable cache coherency protocol Gaurav Garg, Brian P. Lilly, Ramesh Gunna, Steven R. Hutsell, Lital Levy-Rubin +2 more 2024-01-09
11803471 Scalable system on a chip Per Hammarlund, Lior Zimet, Sergio Kolor, Sagi Lahav, Gaurav Garg +11 more 2023-10-31
11768690 Coprocessor context priority Aditya Kesiraju, Andrew J. Beaumont-Smith, Brian P. Lilly, Jason M. Kassoff, Krishna C. Potnuru +4 more 2023-09-26
11720360 DSB operation with excluded region Jeff Gonion, John H. Kelm, Pradeep Kanapathipillai, Mridul Agarwal, Gideon N. Levinsky +2 more 2023-08-08
11675722 Multiple independent on-chip interconnect Sergio Kolor, Sergio V. Tota, Tzach Zemer, Sagi Lahav, Jonathan Redshaw +8 more 2023-06-13
11544193 Scalable cache coherency protocol Gaurav Garg, Brian P. Lilly, Ramesh Gunna, Steven R. Hutsell, Lital Levy-Rubin +2 more 2023-01-03
11500638 Hardware compression and decompression engine Aditya Kesiraju, Pradeep Kanapathipillai, Mridul Agarwal, Zhaoming Hu, Tyler J. Huberty +1 more 2022-11-15
11210104 Coprocessor context priority Aditya Kesiraju, Andrew J. Beaumont-Smith, Brian P. Lilly, Jason M. Kassoff, Krishna C. Potnuru +4 more 2021-12-28
10795818 Method and apparatus for ensuring real-time snoop latency Harshavardhan Kaushikkar, Per Hammarlund, Brian P. Lilly, Michael Bekerman, Manu Gulati +1 more 2020-10-06
10725919 Processors having virtually clustered cores and cache slices Herbert Hum, Brinda Ganesh, Ganesh Kumar, Leena K. Puthiyedath, Scott J. Erlanger +6 more 2020-07-28
10725920 Processors having virtually clustered cores and cache slices Herbert Hum, Brinda Ganesh, Ganesh Kumar, Leena K. Puthiyedath, Scott J. Erlanger +6 more 2020-07-28
10705960 Processors having virtually clustered cores and cache slices Herbert Hum, Brinda Ganesh, Ganesh Kumar, Leena K. Puthiyedath, Scott J. Erlanger +6 more 2020-07-07
10127153 Cache dependency handling Prashant Jain, Sandeep Gupta 2018-11-13
10073779 Processors having virtually clustered cores and cache slices Herbert Hum, Brinda Ganesh, Ganesh Kumar, Leena K. Puthiyedath, Scott J. Erlanger +6 more 2018-09-11
10019366 Satisfying memory ordering requirements between partial reads and non-snoop accesses Robert Beers, Ching-Tsun Chou, Robert J. Safranek 2018-07-10
9703712 Satisfying memory ordering requirements between partial reads and non-snoop accesses Robert Beers, Ching-Tsun Chou, Robert J. Safranek 2017-07-11