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USPTO Patent Rankings Data through Dec 31, 2025
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Ching-Tsun Chou — 13 Patents

Intel: 12 patents #3,451 of 30,777Top 15%
Palo Alto, CA: #1,842 of 9,675 inventorsTop 20%
California: #47,433 of 386,348 inventorsTop 15%
Overall (All Time): #362,438 of 4,157,543Top 9%
13 Patents All Time
Ching-Tsun Chou has been granted 13 US patents while listed as an inventor at Intel. The first was granted in 2006 and the most recent in September 2020. Ching-Tsun Chou ranks #362,438 of 4,157,543 US inventors in our database (top 8.7%). Patent records list Ching-Tsun Chou in Palo Alto, CA, US.

Patents per Year

Patents granted per year, 2006 to 2020Bar chart with a peak of 3 patents in 2012.peak 32006: 1 patents20062011: 1 patents20112012: 3 patents20122013: 1 patents20132014: 2 patents20142015: 1 patents20152017: 1 patents20172018: 2 patents20182020: 1 patents2020

Issued Patents All Time

Showing 1–13 of 13 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
10761849 Processors, methods, systems, and instruction conversion modules for instructions with compact instruction encodings due to use of context of a prior instruction Oleg Margulis, Tyler Sondag 2020-09-01 $24,773,000
10120686 Eliminating redundant store instructions from execution while maintaining total store order Vineeth Mekkat, Oleg Margulis, Youfeng Wu 2018-11-06 $18,970,000
10019366 Satisfying memory ordering requirements between partial reads and non-snoop accesses Robert Beers, Robert J. Safranek, James Vash 2018-07-10 $30,438,000
9703712 Satisfying memory ordering requirements between partial reads and non-snoop accesses Robert Beers, Robert J. Safranek, James Vash 2017-07-11 $8,311,000
9058271 Satisfying memory ordering requirements between partial reads and non-snoop accesses Robert Beers, Robert J. Safranek, James Vash 2015-06-16 $24,798,000
8694736 Satisfying memory ordering requirements between partial reads and non-snoop accesses Robert Beers, Robert J. Safranek, James Vash 2014-04-08 $30,134,000
8693319 Scheme for avoiding deadlock in multi-ring interconnect, with additional application to congestion control Naveen Cherukuri 2014-04-08 $30,134,000
8443337 Methodology and tools for tabled-based protocol specification and model generation Phanindra Kumar Mannava, Seungjoon Park 2013-05-14 $17,697,000
8250311 Satisfying memory ordering requirements between partial reads and non-snoop accesses Robert Beers, Robert J. Safranek, James Vash 2012-08-21 $17,627,000
8205045 Satisfying memory ordering requirements between partial writes and non-snoop accesses Robert Beers, Robert J. Safranek 2012-06-19 $20,138,000
8099558 Fairness mechanism for starvation prevention in directory-based cache coherence protocols Seungjoon Park, Akhilesh Kumar 2012-01-17
7991875 Link level retry scheme Suresh Chittor, Andalib Khan, Akhilesh Kumar, Phanindra Kumar Mannava, Rajee Ram +3 more 2011-08-02 $15,238,000
7016304 Link level retry scheme Suresh Chittor, Andalib Khan, Akhilesh Kumar, Phanindra Kumar Mannava, Rajee Ram +3 more 2006-03-21 $17,683,000