Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12216581 | System, method, and apparatus for enhanced pointer identification and prefetching | Sreenivas Subramoney, Stanislav Shwartsman, Anant Vithal Nori, Shankar Balachandran, Elad Shtiegmann +2 more | 2025-02-04 |
| 11693780 | System, method, and apparatus for enhanced pointer identification and prefetching | Sreenivas Subramoney, Stanislav Shwartsman, Anant Vithal Nori, Shankar Balachandran, Elad Shtiegmann +2 more | 2023-07-04 |
| 11080194 | System, method, and apparatus for enhanced pointer identification and prefetching | Sreenivas Subramoney, Stanislav Shwartsman, Anant Vithal Nori, Shankar Balachandran, Elad Shtiegmann +2 more | 2021-08-03 |
| 10915320 | Shift-folding for efficient load coalescing in a binary translation based processor | Xi Chen, Manjunath Shevgoor | 2021-02-09 |
| 10853078 | Method and apparatus for supporting speculative memory optimizations | Mark Dechene, Zhongying Zhang, John W. Faistl, Janghaeng Lee, Hou-Jen Ko +2 more | 2020-12-01 |
| 10540178 | Eliminating redundant stores using a protection designator and a clear designator | Youfeng Wu, Sebastian Winkel, Oleg Margulis | 2020-01-21 |
| 10296343 | Hybrid atomicity support for a binary translation based microprocessor | Jason M. Agron, Youfeng Wu | 2019-05-21 |
| 10235177 | Register reclamation | Janghaeng Lee, Youfeng Wu | 2019-03-19 |
| 10228956 | Supporting binary translation alias detection in an out-of-order processor | Mark Dechene, Zhongying Zhang, Jason M. Agron, Sebastian Winkel | 2019-03-12 |
| 10120686 | Eliminating redundant store instructions from execution while maintaining total store order | Oleg Margulis, Ching-Tsun Chou, Youfeng Wu | 2018-11-06 |
| 9996356 | Method and apparatus for recovering from bad store-to-load forwarding in an out-of-order processor | Oleg Margulis, Jason M. Agron, Ethan Schuchman, Sebastian Winkel, Youfeng Wu +1 more | 2018-06-12 |
| 9916164 | Methods and apparatus to optimize instructions for execution by a processor | Girish Venkatasubramanian, Howard H. Chen | 2018-03-13 |
| 9710389 | Method and apparatus for memory aliasing detection in an out-of-order instruction execution platform | Oleg Margulis, Sumit Ahuja, Polychronis Xekalakis, Yongjun Park, Igor Yanover +2 more | 2017-07-18 |