Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12169718 | Systems, methods and apparatus for speculative elimination of load instruction | Vineeth Thamarassery Mekkat, Rangeen Basu Roy Chowdhury | 2024-12-17 |
| 11934809 | Multi-stage automatic compilation for vector computations in applications | Junyong Ding, Mohammad R. Haghighat, Qi Zhang, Tianyou Li | 2024-03-19 |
| 10884735 | Instruction and logic for predication and implicit destination | Jayesh Iyer, Jamison D. Collins, Howard H. Chen | 2021-01-05 |
| 10877765 | Apparatuses and methods to assign a logical thread to a physical thread | Ethan Schuchman, Rainer Theuer, Gregor Stellpflug, Tyler Sondag | 2020-12-29 |
| 10853078 | Method and apparatus for supporting speculative memory optimizations | Vineeth Mekkat, Mark Dechene, Zhongying Zhang, John W. Faistl, Janghaeng Lee +2 more | 2020-12-01 |
| 10540178 | Eliminating redundant stores using a protection designator and a clear designator | Vineeth Mekkat, Youfeng Wu, Oleg Margulis | 2020-01-21 |
| 10346170 | Performing partial register write operations in a processor | Jayesh Iyer, Jamison D. Collins | 2019-07-09 |
| 10324724 | Hardware apparatuses and methods to fuse instructions | Patrick P. Lai, Tyler Sondag, Polychronis Xekalakis, Ethan Schuchman, Jayesh Iyer | 2019-06-18 |
| 10228956 | Supporting binary translation alias detection in an out-of-order processor | Vineeth Mekkat, Mark Dechene, Zhongying Zhang, Jason M. Agron | 2019-03-12 |
| 10216516 | Fused adjacent memory stores | Jamison D. Collins, Tyler Sondag | 2019-02-26 |
| 10083033 | Apparatus and method for efficient register allocation and reclamation | Girish Venkatasubramanian, Tyler Sondag, Rolf Kassa | 2018-09-25 |
| 10055256 | Instruction and logic for scheduling instructions | Ethan Schuchman, Tyler Sondag, Girish Venkatasubramanian | 2018-08-21 |
| 9996356 | Method and apparatus for recovering from bad store-to-load forwarding in an out-of-order processor | Vineeth Mekkat, Oleg Margulis, Jason M. Agron, Ethan Schuchman, Youfeng Wu +1 more | 2018-06-12 |
| 9904546 | Instruction and logic for predication and implicit destination | Jayesh Iyer, Jamison D. Collins, Howard H. Chen | 2018-02-27 |
| 9710389 | Method and apparatus for memory aliasing detection in an out-of-order instruction execution platform | Oleg Margulis, Sumit Ahuja, Polychronis Xekalakis, Yongjun Park, Vineeth Mekkat +2 more | 2017-07-18 |
| 9524170 | Instruction and logic for memory disambiguation in an out-of-order processor | Rainer Theur, Arun Raman, Jaroslaw Topp, Rakesh Ranjan, Gregor Stellpflug +1 more | 2016-12-20 |
| 9274799 | Instruction and logic for scheduling instructions | Ethan Schuchman, Tyler Sondag, Girish Venkatasubramanian | 2016-03-01 |
| 9116729 | Handling of binary translated self modifying code and cross modifying code | Nirajan L. Cooray, David Keppel, Naveen Kumar, Ori Lempel, Michael Neilly +2 more | 2015-08-25 |
| 8775153 | Transitioning from source instruction set architecture (ISA) code to translated code in a partial emulation environment | Koichi Yamada, Suresh Srinivas, James E. Smith | 2014-07-08 |
| 8762127 | Transitioning from source instruction set architecture (ISA) code to translated code in a partial emulation environment | Koichi Yamada, Suresh Srinivas, James E. Smith | 2014-06-24 |