Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11715019 | Method and device for operating a neural network in a memory-efficient manner | Andre Guntoro, Armin Runge, Christoph Schorn, Sebastian Vogel, Juergen Schirmer | 2023-08-01 |
| 11698672 | Selective deactivation of processing units for artificial neural networks | Juergen Schirmer, Andre Guntoro, Armin Runge, Christoph Schorn, Sebastian Vogel | 2023-07-11 |
| 11593232 | Method and device for verifying a neuron function in a neural network | Andre Guntoro, Armin Runge, Christoph Schorn, Sebastian Vogel, Juergen Schirmer | 2023-02-28 |
| 10409763 | Apparatus and method for efficiently implementing a processor pipeline | Patrick P. Lai, Ethan Schuchman, David Keppel, Denis M. Khartikov, Polychronis Xekalakis +7 more | 2019-09-10 |
| 10384689 | Method for operating a control unit | Dieter Thoss, Margit Mueller, Thomas Hartgen | 2019-08-20 |
| 10157062 | Method for operating a microprocessor | — | 2018-12-18 |
| 9973417 | Method and apparatus for managing application state in a network interface controller in a high performance computing system | Keith D. Underwood, Steffen Kosinski, Jan Norden, Michael Redeker | 2018-05-15 |
| 9582432 | Instruction and logic for support of code modification in translation lookaside buffers | Niranjan L. Cooray, Fernando Latorre | 2017-02-28 |
| 9558121 | Two-level cache locking mechanism | Li-Gao Zei, Fernando Latorre, Steffen Kosinski, Varun K. Mohandru, Lutz Naethke | 2017-01-31 |
| 9524170 | Instruction and logic for memory disambiguation in an out-of-order processor | Rainer Theur, Arun Raman, Rakesh Ranjan, Sebastian Winkel, Gregor Stellpflug +1 more | 2016-12-20 |
| 9436651 | Method and apparatus for managing application state in a network interface controller in a high performance computing system | Keith D. Underwood, Steffen Kosinski, Jan Uerpmann, Michael Redeker | 2016-09-06 |
| 9367477 | Instruction and logic for support of code modification in translation lookaside buffers | Niranjan L. Cooray, Fernando Latorre | 2016-06-14 |
| 9311239 | Power efficient level one data cache access with pre-validated tags | Niranjan L. Cooray, Steffen Kosinski, Rami May, Doron Gershon, Varun K. Mohandru | 2016-04-12 |
| 9158705 | Stride-based translation lookaside buffer (TLB) prefetching with adaptive offset | Pedro Lopez, Fernando Latorre, Demos Pavlou, Thang Vu | 2015-10-13 |
| 9009413 | Method and apparatus to implement lazy flush in a virtually tagged cache memory | Varun K. Mohandru, Fernando Latorre, Niranjan L. Cooray, Pedro Lopez, Naveen Neelakantam +3 more | 2015-04-14 |