Issued Patents All Time
Showing 25 most recent of 38 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12405727 | Method and apparatus for data buffering of write operations and performing write operations | Lawrence C. Stewart | 2025-09-02 |
| 12242753 | Reduced network load with combined put or get and receiver-managed offset | David Ozog | 2025-03-04 |
| 11989135 | Programmable address range engine for larger region sizes | Farah E. FARGO, Mitchell Diamond, Samantika S. Sury, Binh Pham, Shobha Vissapragada | 2024-05-21 |
| 11055232 | Valid bits of a translation lookaside buffer (TLB) for checking multiple page sizes in one probe cycle and reconfigurable sub-TLBS | Binh Pham | 2021-07-06 |
| 10771404 | Performance monitoring | Thomas D. Lovett, Michael A. Parker, Robert C. Zak | 2020-09-08 |
| 10409763 | Apparatus and method for efficiently implementing a processor pipeline | Patrick P. Lai, Ethan Schuchman, Denis M. Khartikov, Polychronis Xekalakis, Joshua B. Fryman +7 more | 2019-09-10 |
| 10331550 | Symmetric addressing | Charles J. Archer | 2019-06-25 |
| 10200310 | Fabric-integrated data pulling engine | James Dinan, Mario Flajslik, Keith D. Underwood, Ulf Hanebutte | 2019-02-05 |
| 10178041 | Technologies for aggregation-based message synchronization | James Dinan, Mario Flajslik, Ulf Hanebutte | 2019-01-08 |
| 10168765 | Controlling processor consumption using on-off keying having a maxiumum off time | Jawad Nasrullah | 2019-01-01 |
| 10135708 | Technologies for performance inspection at an endpoint node | James Dinan | 2018-11-20 |
| 10135711 | Technologies for sideband performance tracing of network traffic | Robert C. Zak, James Dinan | 2018-11-20 |
| 10061587 | Instruction and logic for bulk register reclamation | Denis M. Khartikov, Fernando Latorre, Marc Lupon, Grigorios Magklis, Naveen Neelakantam +2 more | 2018-08-28 |
| 10061376 | Opportunistic power management for managing intermittent power available to data processing device having semi-non-volatile memory or non-volatile memory | Helia Naeimi | 2018-08-28 |
| 9971599 | Instruction and logic for support of code modification | John H. Kelm, David N. Mackintosh | 2018-05-15 |
| 9965023 | Apparatus and method for flushing dirty cache lines based on cache activity levels | Kelvin Kwan, Jawad Nasrullah | 2018-05-08 |
| 9766685 | Controlling power consumption of a processor using interrupt-mediated on-off keying | Jawad Nasrullah | 2017-09-19 |
| 9652268 | Instruction and logic for support of code modification | John H. Kelm, David N. Mackintosh | 2017-05-16 |
| 9477628 | Collective communications apparatus and method for parallel systems | Allan D. Knies, Dong Hyuk Woo, Joshua B. Fryman | 2016-10-25 |
| 9442849 | Apparatus and method for reduced core entry into a power state having a powered down core cache | Kelvin Kwan, Jawad Nasrullah | 2016-09-13 |
| 9354694 | Controlling processor consumption using on-off keying having a maximum off time | Jawad Nasrullah | 2016-05-31 |
| 9342403 | Method and apparatus for managing a spin transfer torque memory | Helia Naeimi, Jawad Nasrullah | 2016-05-17 |
| 9329658 | Block-level sleep logic | Jawad Nasrullah | 2016-05-03 |
| 9116729 | Handling of binary translated self modifying code and cross modifying code | Nirajan L. Cooray, Naveen Kumar, Ori Lempel, Michael Neilly, Naveen Neelakantam +2 more | 2015-08-25 |
| 8418153 | Method for integration of interpretation and translation in a microprocessor | Robert Bedichek, Linus Torvalds | 2013-04-09 |