UH

Ulf Hanebutte

Disney: 25 patents #238 of 6,686Top 4%
IN Intel: 14 patents #2,910 of 30,777Top 10%
Overall (All Time): #80,375 of 4,157,543Top 2%
39
Patents All Time

Issued Patents All Time

Showing 25 most recent of 39 patents

Patent #TitleCo-InventorsDate
12430108 Multistage compiler architecture Senad Durakovic, Chien-Chun Chou, Fu-Hwa Wang, Mohana Tandyala 2025-09-30
12293174 Method and system for memory management within machine learning inference engine Nikhil Bernard John Stephen, Senad Durakovic, Chien-Chun Chou, Pranav Jonnalagadda 2025-05-06
12190086 Method and apparatus for ML graphs by a compiler Chien-Chun Chou, Senad Durakovic, Pranav Jonnalagadda 2025-01-07
12174727 Method and apparatus for correlating high-level code with low-level instructions for machine learning applications Harri Hakkarainen, Senad Durakovic, Chien-Chun Chou 2024-12-24
12169719 Instruction set architecture (ISA) format for multiple instruction set architectures in machine learning inference engine Avinash Sodani, Senad Durakovic, Hamid Reza Ghasemi, Chia-Hsin Chen 2024-12-17
12124827 Method and system to expand accessible on-chip memory (OCM) of an inference engine Senad Durakovic, Mohana Tandyala 2024-10-22
12112174 Streaming engine for machine learning architecture Avinash Sodani, Senad Durakovic, Hamid Reza Ghasemi, Chia-Hsin Chen 2024-10-08
12112175 Method and apparatus for performing machine learning operations in parallel on machine learning hardware Avinash Sodani 2024-10-08
11995569 Architecture to support tanh and sigmoid operations for inference acceleration in machine learning Avinash Sodani, Chia-Hsin Chen 2024-05-28
11995448 Method and apparatus for performing machine learning operations in parallel on machine learning hardware Avinash Sodani, Chien-Chun Chou, Harri Hakkarainen 2024-05-28
11977963 System and method for INT9 quantization Avinash Sodani, Chia-Hsin Chen 2024-05-07
11977475 Method and apparatus for compiler and low-level instruction validation of machine learning operations on hardware Chien-Chun Chou, Senad Durakovic, Harri Hakkarainen, Yao-Nan Chou, Veena Karthikeyan 2024-05-07
11733983 Method and apparatus for generating metadata by a compiler Senad Durakovic, Chien-Chun Chou, Harri Hakkarainen 2023-08-22
11551148 System and method for INT9 quantization Avinash Sodani, Chia-Hsin Chen 2023-01-10
11494676 Architecture for table-based mathematical operations for inference acceleration in machine learning Avinash Sodani, Chia-Hsin Chen 2022-11-08
11467811 Method and apparatus for generating metadata by a compiler Senad Durakovic, Chien-Chun Chou, Harri Hakkarainen 2022-10-11
11301247 System and method for handling floating point hardware exception Chia-Hsin Chen, Avinash Sodani, Rishan Tan, Soumya Gollamudi 2022-04-12
11256517 Architecture of crossbar of inference engine Avinash Sodani, Senad Durakovic, Hamid Reza Ghasemi, Chia-Hsin Chen 2022-02-22
11086633 Single instruction set architecture (ISA) format for multiple ISAS in machine learning inference engine Avinash Sodani, Senad Durakovic, Hamid Reza Ghasemi, Chia-Hsin Chen 2021-08-10
11029963 Architecture for irregular operations in machine learning inference engine Avinash Sodani, Senad Durakovic, Hamid Reza Ghasemi, Chia-Hsin Chen, Rishan Tan 2021-06-08
10997510 Architecture to support tanh and sigmoid operations for inference acceleration in machine learning Avinash Sodani, Chia-Hsin Chen 2021-05-04
10970080 Systems and methods for programmable hardware architecture for machine learning Avinash Sodani, Chia-Hsin Chen, Hamid Reza Ghasemi, Senad Durakovic 2021-04-06
10929760 Architecture for table-based mathematical operations for inference acceleration in machine learning Avinash Sodani, Chia-Hsin Chen 2021-02-23
10896045 Architecture for dense operations in machine learning inference engine Avinash Sodani, Senad Durakovic, Hamid Reza Ghasemi, Chia-Hsin Chen 2021-01-19
10824433 Array-based inference engine for machine learning Avinash Sodani, Senad Durakovic, Hamid Reza Ghasemi, Chia-Hsin Chen 2020-11-03