Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12430108 | Multistage compiler architecture | Ulf Hanebutte, Chien-Chun Chou, Fu-Hwa Wang, Mohana Tandyala | 2025-09-30 |
| 12293174 | Method and system for memory management within machine learning inference engine | Nikhil Bernard John Stephen, Chien-Chun Chou, Pranav Jonnalagadda, Ulf Hanebutte | 2025-05-06 |
| 12190086 | Method and apparatus for ML graphs by a compiler | Ulf Hanebutte, Chien-Chun Chou, Pranav Jonnalagadda | 2025-01-07 |
| 12174727 | Method and apparatus for correlating high-level code with low-level instructions for machine learning applications | Ulf Hanebutte, Harri Hakkarainen, Chien-Chun Chou | 2024-12-24 |
| 12169719 | Instruction set architecture (ISA) format for multiple instruction set architectures in machine learning inference engine | Avinash Sodani, Ulf Hanebutte, Hamid Reza Ghasemi, Chia-Hsin Chen | 2024-12-17 |
| 12124827 | Method and system to expand accessible on-chip memory (OCM) of an inference engine | Ulf Hanebutte, Mohana Tandyala | 2024-10-22 |
| 12112174 | Streaming engine for machine learning architecture | Avinash Sodani, Ulf Hanebutte, Hamid Reza Ghasemi, Chia-Hsin Chen | 2024-10-08 |
| 11995463 | Architecture to support color scheme-based synchronization for machine learning | Avinash Sodani, Gopal Nalamalapu | 2024-05-28 |
| 11977475 | Method and apparatus for compiler and low-level instruction validation of machine learning operations on hardware | Chien-Chun Chou, Ulf Hanebutte, Harri Hakkarainen, Yao-Nan Chou, Veena Karthikeyan | 2024-05-07 |
| 11733983 | Method and apparatus for generating metadata by a compiler | Chien-Chun Chou, Ulf Hanebutte, Harri Hakkarainen | 2023-08-22 |
| 11467811 | Method and apparatus for generating metadata by a compiler | Chien-Chun Chou, Ulf Hanebutte, Harri Hakkarainen | 2022-10-11 |
| 11256517 | Architecture of crossbar of inference engine | Avinash Sodani, Ulf Hanebutte, Hamid Reza Ghasemi, Chia-Hsin Chen | 2022-02-22 |
| 11086633 | Single instruction set architecture (ISA) format for multiple ISAS in machine learning inference engine | Avinash Sodani, Ulf Hanebutte, Hamid Reza Ghasemi, Chia-Hsin Chen | 2021-08-10 |
| 11029963 | Architecture for irregular operations in machine learning inference engine | Avinash Sodani, Ulf Hanebutte, Hamid Reza Ghasemi, Chia-Hsin Chen, Rishan Tan | 2021-06-08 |
| 11016801 | Architecture to support color scheme-based synchronization for machine learning | Avinash Sodani, Gopal Nalamalapu | 2021-05-25 |
| 10970080 | Systems and methods for programmable hardware architecture for machine learning | Avinash Sodani, Chia-Hsin Chen, Ulf Hanebutte, Hamid Reza Ghasemi | 2021-04-06 |
| 10896045 | Architecture for dense operations in machine learning inference engine | Avinash Sodani, Ulf Hanebutte, Hamid Reza Ghasemi, Chia-Hsin Chen | 2021-01-19 |
| 10824433 | Array-based inference engine for machine learning | Avinash Sodani, Ulf Hanebutte, Hamid Reza Ghasemi, Chia-Hsin Chen | 2020-11-03 |