Issued Patents All Time
Showing 25 most recent of 75 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12292978 | System and method for SRAM less electronic device bootup using cache | Ramacharan Sundararaman | 2025-05-06 |
| 12169719 | Instruction set architecture (ISA) format for multiple instruction set architectures in machine learning inference engine | Ulf Hanebutte, Senad Durakovic, Hamid Reza Ghasemi, Chia-Hsin Chen | 2024-12-17 |
| 12112174 | Streaming engine for machine learning architecture | Ulf Hanebutte, Senad Durakovic, Hamid Reza Ghasemi, Chia-Hsin Chen | 2024-10-08 |
| 12112175 | Method and apparatus for performing machine learning operations in parallel on machine learning hardware | Ulf Hanebutte | 2024-10-08 |
| 11995448 | Method and apparatus for performing machine learning operations in parallel on machine learning hardware | Ulf Hanebutte, Chien-Chun Chou, Harri Hakkarainen | 2024-05-28 |
| 11995569 | Architecture to support tanh and sigmoid operations for inference acceleration in machine learning | Ulf Hanebutte, Chia-Hsin Chen | 2024-05-28 |
| 11994925 | Power management and staggering transitioning from idle mode to operational mode | Srinivas Sripada, Chia-Hsin Chen, Atul Bhattarai, Nikhil Jayakumar | 2024-05-28 |
| 11995463 | Architecture to support color scheme-based synchronization for machine learning | Senad Durakovic, Gopal Nalamalapu | 2024-05-28 |
| 11977963 | System and method for INT9 quantization | Ulf Hanebutte, Chia-Hsin Chen | 2024-05-07 |
| 11927932 | System and method to manage power to a desired power profile | Ramacharan Sundararaman, James G. Eldredge, Richard K. Taylor | 2024-03-12 |
| 11868475 | System and methods for latency reduction for fuse reload post reset | Ramacharan Sundararaman, Nithyananda Miyar, Martin Kovac, Raghuveer Shivaraj | 2024-01-09 |
| 11842197 | System and methods for tag-based synchronization of tasks for machine learning operations | Gopal Nalamalapu | 2023-12-12 |
| 11829492 | System and method for hardware-based register protection mechanism | Ramacharan Sundararaman, Saurabh Shrivastava, Nithyananda Miyar | 2023-11-28 |
| 11789513 | Power management and current/ramp detection mechanism | Atul Bhattarai, Srinivas Sripada, Michael Dudek, Darren Jay Walworth, Roshan Fernando +2 more | 2023-10-17 |
| 11734608 | Address interleaving for machine learning | Ramacharan Sundararaman | 2023-08-22 |
| 11687136 | System and method to manage power throttling | Srinivas Sripada, Ramacharan Sundararaman, Chia-Hsin Chen, Nikhil Jayakumar | 2023-06-27 |
| 11687837 | Architecture to support synchronization between core and inference engine for machine learning | Gopal Nalamalapu | 2023-06-27 |
| 11635739 | System and method to manage power to a desired power profile | Ramacharan Sundararaman, James G. Eldredge, Richard K. Taylor | 2023-04-25 |
| 11621923 | Queueing system with head-of-line block avoidance | Enric Musoll, Dan Tu, Chia-Hsin Chen | 2023-04-04 |
| 11604683 | System and methods for tag-based synchronization of tasks for machine learning operations | Gopal Nalamalapu | 2023-03-14 |
| 11551148 | System and method for INT9 quantization | Ulf Hanebutte, Chia-Hsin Chen | 2023-01-10 |
| 11526204 | Power management and transitioning cores within a multicore system from idle mode to operational mode over a period of time | Chia-Hsin Chen, Atul Bhattarai, Srinivas Sripada | 2022-12-13 |
| 11526440 | Providing multiple memory modes for a processor including internal memory | Robert J. Kyanko, Richard J. Greco, Andreas Kleen, Milind B. Girkar, Christopher M. Cantalupo | 2022-12-13 |
| 11507170 | Power management and current/ramp detection mechanism | Atul Bhattarai, Srinivas Sripada, Michael Dudek, Darren Jay Walworth, Roshan Fernando +2 more | 2022-11-22 |
| 11494676 | Architecture for table-based mathematical operations for inference acceleration in machine learning | Ulf Hanebutte, Chia-Hsin Chen | 2022-11-08 |