Issued Patents All Time
Showing 25 most recent of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12430280 | Mechanism to improve the reliability of sideband in chiplets | Ravindranath DODDI, Umamaheshwaran V, Afreen HAIDER, Lekhya Pavani Godavarthi, Harinatha Reddy RAMIREDDY +2 more | 2025-09-30 |
| 12292978 | System and method for SRAM less electronic device bootup using cache | Avinash Sodani | 2025-05-06 |
| 12174757 | Apparatus and methods for reducing latencies associated with link state transitions within die interconnect architectures | Santhosh Reddy AKAVARAM, Prakhar Srivastava, Sridhar ANUMALA, Sonali Jabreva, Khushboo KUMARI +1 more | 2024-12-24 |
| 11927932 | System and method to manage power to a desired power profile | Avinash Sodani, James G. Eldredge, Richard K. Taylor | 2024-03-12 |
| 11921904 | System and methods for firmware security mechanism | Nithyananda Miyar, Martin Kovac | 2024-03-05 |
| 11868475 | System and methods for latency reduction for fuse reload post reset | Nithyananda Miyar, Martin Kovac, Avinash Sodani, Raghuveer Shivaraj | 2024-01-09 |
| 11836501 | System and methods for hardware-based PCIe link up based on post silicon characterization | Nithyananda Miyar | 2023-12-05 |
| 11829492 | System and method for hardware-based register protection mechanism | Saurabh Shrivastava, Avinash Sodani, Nithyananda Miyar | 2023-11-28 |
| 11782866 | Techniques to support mulitple interconnect protocols for an interconnect | Stephen R. Van Doren, Rajesh M. Sankaran, David A. Koufaty, Ishwar Agarwal | 2023-10-10 |
| 11734608 | Address interleaving for machine learning | Avinash Sodani | 2023-08-22 |
| 11729096 | Techniques to support multiple protocols between computer system interconnects | Debendra Das Sharma, Michelle C. Jen, Mark S. Myers, Don Soltis, Stephen R. Van Doren +1 more | 2023-08-15 |
| 11687136 | System and method to manage power throttling | Avinash Sodani, Srinivas Sripada, Chia-Hsin Chen, Nikhil Jayakumar | 2023-06-27 |
| 11635739 | System and method to manage power to a desired power profile | Avinash Sodani, James G. Eldredge, Richard K. Taylor | 2023-04-25 |
| 11586446 | System and methods for hardware-based PCIe link up based on post silicon characterization | Nithyananda Miyar | 2023-02-21 |
| 11340673 | System and method to manage power throttling | Avinash Sodani, Srinivas Sripada, Chia-Hsin Chen, Nikhil Jayakumar | 2022-05-24 |
| 11334258 | System and method for memory region protection | Nithyananda Miyar, Hakseon Lee | 2022-05-17 |
| 11204867 | PCIe controller with extensions to provide coherent memory mapping between accelerator memory and host memory | Ishwar Agarwal, Stephen R. Van Doren | 2021-12-21 |
| 11095556 | Techniques to support multiple protocols between computer system interconnects | Debendra Das Sharma, Michelle C. Jen, Mark S. Myers, Don Soltis, Stephen R. Van Doren +1 more | 2021-08-17 |
| 10929778 | Address interleaving for machine learning | Avinash Sodani | 2021-02-23 |
| 10261904 | Memory sequencing with coherent and non-coherent sub-systems | Chunhui Zhang, George Z. Chrysos, Edward T. Grochowski, Chung-Lun Chan, Federico Ardanaz | 2019-04-16 |
| 9875185 | Memory sequencing with coherent and non-coherent sub-systems | Chunhui Zhang, George Z. Chrysos, Edward T. Grochowski, Chung-Lun Chan, Federico Ardanaz | 2018-01-23 |
| 9785556 | Cross-die interface snoop or global observation message ordering | Tracey L. Gustafson, Robert J. Safranek | 2017-10-10 |
| 9658861 | Boot strap processor assignment for a multi-core processing unit | Steven Chang, Anshuman Thakur, Ramon Matas, Jay S. Lawlor, Robert F. Netting | 2017-05-23 |
| 9430389 | Prefetch with request for ownership without data | Jesus Corbal, Lisa K. Wu, George Z. Chrysos, Andrew T. Forsyth | 2016-08-30 |
| 9389657 | Reset of multi-core processing system | Steven Chang, Anshuman Thakur, Ramon Matas | 2016-07-12 |