Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12430280 | Mechanism to improve the reliability of sideband in chiplets | Ravindranath DODDI, Umamaheshwaran V, Afreen HAIDER, Lekhya Pavani Godavarthi, James Lionel Panian +2 more | 2025-09-30 |
| 12386382 | Reduced training for main band chip module interconnection clock lines | Lekhya Pavani Godavarthi, Ravindranath DODDI, Afreen HAIDER, Umamaheshwaran V | 2025-08-12 |
| 12380047 | Expanded data link width for main band chip module connection in alternate modes | Ravindranath DODDI, Umamaheshwaran V, Afreen HAIDER, Lekhya Pavani Godavarthi | 2025-08-05 |
| 12314204 | Single clock lane operation for a main band of a die-to-die connection | Ravindranath DODDI, Lekhya Pavani Godavarthi, Umamaheshwaran V, Afreen HAIDER | 2025-05-27 |