| 12430280 |
Mechanism to improve the reliability of sideband in chiplets |
Umamaheshwaran V, Afreen HAIDER, Lekhya Pavani Godavarthi, Harinatha Reddy RAMIREDDY, James Lionel Panian +2 more |
2025-09-30 |
| 12430199 |
Flow control between peripheral component interconnect express devices |
Santhosh Reddy AKAVARAM, Prakhar Srivastava, Sai Sreeja Mukka, Yogananda Rao Chillariga |
2025-09-30 |
| 12423252 |
Systems and methods for reducing latency and improving performance in a peripheral component interconnect express (PCIe) system |
Surendra Paravada, Madhu Yashwanth Boenapalli, Vinod Kumar Kuruma, Sai Praneeth Sreeram |
2025-09-23 |
| 12417196 |
Systems and methods for reducing latency and power consumption in a peripheral component interconnect express (PCIe) system |
Madhu Yashwanth Boenapalli, Vinod Kumar Kuruma, Surendra Paravada, Sai Praneeth Sreeram |
2025-09-16 |
| 12399853 |
Mechanism to improve link initialization time |
Santhosh Reddy AKAVARAM, Prakhar Srivastava, Umamaheshwaran V, Ravi Kumar SEPURI |
2025-08-26 |
| 12386382 |
Reduced training for main band chip module interconnection clock lines |
Lekhya Pavani Godavarthi, Harinatha Reddy RAMIREDDY, Afreen HAIDER, Umamaheshwaran V |
2025-08-12 |
| 12380047 |
Expanded data link width for main band chip module connection in alternate modes |
Umamaheshwaran V, Afreen HAIDER, Lekhya Pavani Godavarthi, Harinatha Reddy RAMIREDDY |
2025-08-05 |
| 12373359 |
Mechanism to enhance PCIe generation switching |
Santhosh Reddy AKAVARAM, Prakhar Srivastava, Rajendra Varma Pusapati, Sonali Jabreva |
2025-07-29 |
| 12314204 |
Single clock lane operation for a main band of a die-to-die connection |
Lekhya Pavani Godavarthi, Umamaheshwaran V, Afreen HAIDER, Harinatha Reddy RAMIREDDY |
2025-05-27 |
| 12164448 |
Mechanism to reduce exit latency for deeper power saving modes L2 in PCIe |
Santhosh Reddy AKAVARAM, Prakhar Srivastava |
2024-12-10 |
| 12153527 |
Data rate increase for faulty lane recovery in multiple lane data links |
Santhosh Reddy AKAVARAM, Prakhar Srivastava, Rajendra Varma Pusapati, Yogananda Rao Chillariga |
2024-11-26 |
| 12079061 |
Power management for peripheral component interconnect |
Prakhar Srivastava, Santhosh Reddy AKAVARAM, Ravi Kumar SEPURI |
2024-09-03 |
| 12019577 |
Latency reduction for link speed switching in multiple lane data links |
Prakhar Srivastava, Santhosh Reddy AKAVARAM, Ravi Kumar SEPURI |
2024-06-25 |
| 11934335 |
Power management for peripheral component interconnect |
Prakhar Srivastava, Santhosh Reddy AKAVARAM |
2024-03-19 |