Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12430280 | Mechanism to improve the reliability of sideband in chiplets | Ravindranath DODDI, Umamaheshwaran V, Afreen HAIDER, Lekhya Pavani Godavarthi, Harinatha Reddy RAMIREDDY +2 more | 2025-09-30 |
| 12430199 | Flow control between peripheral component interconnect express devices | Prakhar Srivastava, Sai Sreeja Mukka, Yogananda Rao Chillariga, Ravindranath DODDI | 2025-09-30 |
| 12417023 | Host device caching of flash memory address mappings | Pratibind Kumar JHA, Manish Garg, Prakhar Srivastava, Hung Vuong, Abhishek Ghosh +1 more | 2025-09-16 |
| 12399853 | Mechanism to improve link initialization time | Ravindranath DODDI, Prakhar Srivastava, Umamaheshwaran V, Ravi Kumar SEPURI | 2025-08-26 |
| 12393479 | Exception event handling in flash memory system | Sai Naresh GAJAPAKA, Radhakrishna MUGADA, Chintalapati BHARATH SAI VARMA, Sridhar ANUMALA | 2025-08-19 |
| 12373359 | Mechanism to enhance PCIe generation switching | Prakhar Srivastava, Ravindranath DODDI, Rajendra Varma Pusapati, Sonali Jabreva | 2025-07-29 |
| 12332825 | Apparatus and method for configuring a interconnect link between chiplets | Prakhar Srivastava, Aditya Patel, Ravi Kumar SEPURI | 2025-06-17 |
| 12282392 | Interconnects between chiplets and related link initialization protocols | Prakhar Srivastava, Aditya Patel, Yogananda Rao Chillariga | 2025-04-22 |
| 12271303 | System and method for updating memory tables | Manish Garg, Pratibind Kumar JHA, Prakhar Srivastava | 2025-04-08 |
| 12197775 | Memory devices write buffer management | Sonali Jabreva, Prakhar Srivastava, Surendra Paravada, Yogananda Rao Chillariga, Madhu Yashwanth Boenapalli | 2025-01-14 |
| 12174757 | Apparatus and methods for reducing latencies associated with link state transitions within die interconnect architectures | Prakhar Srivastava, Sridhar ANUMALA, Ramacharan Sundararaman, Sonali Jabreva, Khushboo KUMARI +1 more | 2024-12-24 |
| 12164448 | Mechanism to reduce exit latency for deeper power saving modes L2 in PCIe | Ravindranath DODDI, Prakhar Srivastava | 2024-12-10 |
| 12153527 | Data rate increase for faulty lane recovery in multiple lane data links | Prakhar Srivastava, Rajendra Varma Pusapati, Ravindranath DODDI, Yogananda Rao Chillariga | 2024-11-26 |
| 12079061 | Power management for peripheral component interconnect | Prakhar Srivastava, Ravindranath DODDI, Ravi Kumar SEPURI | 2024-09-03 |
| 12056364 | Write buffer and logical unit management in a data storage device | Yogananda Rao Chillariga, Prakhar Srivastava, Sonali Jabreva, Chintalapati BHARATH SAI VARMA | 2024-08-06 |
| 12019577 | Latency reduction for link speed switching in multiple lane data links | Prakhar Srivastava, Ravindranath DODDI, Ravi Kumar SEPURI | 2024-06-25 |
| 11934335 | Power management for peripheral component interconnect | Prakhar Srivastava, Ravindranath DODDI | 2024-03-19 |