Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12033903 | High-density microbump and probe pad arrangement for semiconductor components | — | 2024-07-09 |
| 11994925 | Power management and staggering transitioning from idle mode to operational mode | Srinivas Sripada, Chia-Hsin Chen, Avinash Sodani, Atul Bhattarai | 2024-05-28 |
| 11687136 | System and method to manage power throttling | Avinash Sodani, Srinivas Sripada, Ramacharan Sundararaman, Chia-Hsin Chen | 2023-06-27 |
| 11340673 | System and method to manage power throttling | Avinash Sodani, Srinivas Sripada, Ramacharan Sundararaman, Chia-Hsin Chen | 2022-05-24 |
| 10303626 | Approach for chip-level flop insertion and verification based on logic interface definition | Weihuang Wang, Premshanth Theivendran, Gerald Schmidt, Srinath Atluri | 2019-05-28 |
| 10198389 | Baseboard interconnection device, system and method | Amir H. Motamedi, Bhagavathi R. Mula, Vivek Trivedi, Vasant K. Palisetti, Daman Ahluwalia | 2019-02-05 |
| 9792400 | Determination of flip-flop count in physical design | Chirinjeev Singh, Weihuang Wang, Weinan Ma, Daman Ahluwalia | 2017-10-17 |
| 9600614 | Automated flip-flop insertions in physical design without perturbation of routing | Weihuang Wang, Weinan Ma, Daman Ahluwalia, Chirinjeev Singh | 2017-03-21 |
| 9600620 | Repeater insertions providing reduced routing perturbation caused by flip-flop insertions | Daman Ahluwalia | 2017-03-21 |
| 9443053 | System for and method of placing clock stations using variable drive-strength clock drivers built out of a smaller subset of base cells for hybrid tree-mesh clock distribution networks | Vivek Trivedi, Vasant K. Palisetti, Bhagavati R. Mula, Daman Ahluwalia, Amir H. Motamedi | 2016-09-13 |
| 9390209 | System for and method of combining CMOS inverters of multiple drive strengths to create tune-able clock inverters of variable drive strengths in hybrid tree-mesh clock distribution networks | Vivek Trivedi, Vasant K. Palisetti, Bhagavati R. Mula, Daman Ahluwalia, Amir H. Motamedi | 2016-07-12 |
| 9305129 | System for and method of tuning clock networks constructed using variable drive-strength clock inverters with variable drive-strength clock drivers built out of a smaller subset of base cells | Vivek Trivedi, Vasant K. Palisetti, Bhagavati R. Mula, Daman Ahluwalia, Amir H. Motamedi | 2016-04-05 |
| 7880505 | Low power reconfigurable circuits with delay compensation | Sunil Khatri, Sheila Vaidya, Timothy Kevin Griffin | 2011-02-01 |