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Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
NJ

Nikhil Jayakumar — 13 Patents

CLCavium, Llc.: 6 patents #54 of 220Top 25%
Disney: 3 patents #2,043 of 6,686Top 35%
XPXpliant: 2 patents #6 of 12Top 50%
Amazon: 1 patents #10,717 of 19,158Top 60%
Sunnyvale, CA: #2,165 of 14,302 inventorsTop 20%
California: #47,433 of 386,348 inventorsTop 15%
Overall (All Time): #362,438 of 4,157,543Top 9%
13 Patents All Time
Nikhil Jayakumar has been granted 13 US patents while listed as an inventor at Cavium, Llc.. The first was granted in 2011 and the most recent in July 2024. Nikhil Jayakumar ranks #362,438 of 4,157,543 US inventors in our database (top 8.7%). Patent records list Nikhil Jayakumar in Sunnyvale, CA, US.

Patents per Year

Patents granted per year, 2011 to 2024Bar chart with a peak of 3 patents in 2016.peak 32011: 1 patents20112016: 3 patents20162017: 3 patents20172019: 2 patents20192022: 1 patents20222023: 1 patents20232024: 2 patents2024

Issued Patents All Time

Showing 1–13 of 13 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12033903 High-density microbump and probe pad arrangement for semiconductor components 2024-07-09 $295,229,000
11994925 Power management and staggering transitioning from idle mode to operational mode Srinivas Sripada, Chia-Hsin Chen, Avinash Sodani, Atul Bhattarai 2024-05-28 $86,617,000
11687136 System and method to manage power throttling Avinash Sodani, Srinivas Sripada, Ramacharan Sundararaman, Chia-Hsin Chen 2023-06-27 $103,381,000
11340673 System and method to manage power throttling Avinash Sodani, Srinivas Sripada, Ramacharan Sundararaman, Chia-Hsin Chen 2022-05-24 $115,863,000
10303626 Approach for chip-level flop insertion and verification based on logic interface definition Weihuang Wang, Premshanth Theivendran, Gerald Schmidt, Srinath Atluri 2019-05-28
10198389 Baseboard interconnection device, system and method Amir H. Motamedi, Bhagavathi R. Mula, Vivek Trivedi, Vasant K. Palisetti, Daman Ahluwalia 2019-02-05
9792400 Determination of flip-flop count in physical design Chirinjeev Singh, Weihuang Wang, Weinan Ma, Daman Ahluwalia 2017-10-17 $32,368,000
9600614 Automated flip-flop insertions in physical design without perturbation of routing Weihuang Wang, Weinan Ma, Daman Ahluwalia, Chirinjeev Singh 2017-03-21
9600620 Repeater insertions providing reduced routing perturbation caused by flip-flop insertions Daman Ahluwalia 2017-03-21
9443053 System for and method of placing clock stations using variable drive-strength clock drivers built out of a smaller subset of base cells for hybrid tree-mesh clock distribution networks Vivek Trivedi, Vasant K. Palisetti, Bhagavati R. Mula, Daman Ahluwalia, Amir H. Motamedi 2016-09-13 $15,926,000
9390209 System for and method of combining CMOS inverters of multiple drive strengths to create tune-able clock inverters of variable drive strengths in hybrid tree-mesh clock distribution networks Vivek Trivedi, Vasant K. Palisetti, Bhagavati R. Mula, Daman Ahluwalia, Amir H. Motamedi 2016-07-12 $7,277,000
9305129 System for and method of tuning clock networks constructed using variable drive-strength clock inverters with variable drive-strength clock drivers built out of a smaller subset of base cells Vivek Trivedi, Vasant K. Palisetti, Bhagavati R. Mula, Daman Ahluwalia, Amir H. Motamedi 2016-04-05 $6,544,000
7880505 Low power reconfigurable circuits with delay compensation Sunil Khatri, Sheila Vaidya, Timothy Kevin Griffin 2011-02-01