Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10198389 | Baseboard interconnection device, system and method | Amir H. Motamedi, Nikhil Jayakumar, Bhagavathi R. Mula, Vivek Trivedi, Daman Ahluwalia | 2019-02-05 |
| 9443053 | System for and method of placing clock stations using variable drive-strength clock drivers built out of a smaller subset of base cells for hybrid tree-mesh clock distribution networks | Nikhil Jayakumar, Vivek Trivedi, Bhagavati R. Mula, Daman Ahluwalia, Amir H. Motamedi | 2016-09-13 |
| 9390209 | System for and method of combining CMOS inverters of multiple drive strengths to create tune-able clock inverters of variable drive strengths in hybrid tree-mesh clock distribution networks | Nikhil Jayakumar, Vivek Trivedi, Bhagavati R. Mula, Daman Ahluwalia, Amir H. Motamedi | 2016-07-12 |
| 9305129 | System for and method of tuning clock networks constructed using variable drive-strength clock inverters with variable drive-strength clock drivers built out of a smaller subset of base cells | Nikhil Jayakumar, Vivek Trivedi, Bhagavati R. Mula, Daman Ahluwalia, Amir H. Motamedi | 2016-04-05 |
| 8347250 | Method and apparatus for addressing and improving holds in logic networks | George A. Gonzalez, Pete J. Hannan, William McGee, Ashok Tirupathy Venkatachar | 2013-01-01 |
| 8266569 | Identification of critical enables using MEA and WAA metrics | Rachida Kebichi, Samuel D. Naffziger | 2012-09-11 |
| 7870521 | Method of designing an electronic device and device thereof | — | 2011-01-11 |