MM

Mark S. Myers

IN Intel: 11 patents #3,700 of 30,777Top 15%
FG Fujitsu Siemens Computers Gmbh: 3 patents #5 of 103Top 5%
BT Ball Aerospace & Technologies: 1 patents #67 of 207Top 35%
Overall (All Time): #219,805 of 4,157,543Top 6%
20
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
11770627 Systems and methods for direct measurement of photon arrival rate Ronald P. Earhart 2023-09-26
11729096 Techniques to support multiple protocols between computer system interconnects Debendra Das Sharma, Michelle C. Jen, Don Soltis, Ramacharan Sundararaman, Stephen R. Van Doren +1 more 2023-08-15
11245604 Techniques to support multiple interconnect protocols for a common set of interconnect connectors Mahesh Wagh, Stephen R. Van Doren, Dimitrios Ziakas, Bassam N. Coury 2022-02-08
11128555 Methods and apparatus for SDI support for automatic and transparent migration Francesc Guim Bernat, Susanne M. Balle, Daniel Rivas Barragan, John Chun Kwok Leung, Suraj Prabhakaran +2 more 2021-09-21
11095556 Techniques to support multiple protocols between computer system interconnects Debendra Das Sharma, Michelle C. Jen, Don Soltis, Ramacharan Sundararaman, Stephen R. Van Doren +1 more 2021-08-17
10884195 Techniques to support multiple interconnect protocols for a common set of interconnect connectors Mahesh Wagh, Stephen R. Van Doren, Dimitrios Ziakas, Bassam N. Coury 2021-01-05
7406632 Error reporting network in multiprocessor computer Charles Sealey, John Lynch, Jason J. Lewis, Stacey G. Lloyd, Paul Kayfes 2008-07-29
7043612 Compute node to mesh interface for highly scalable parallel processing system and method of exchanging data 2006-05-09
6408002 Torus routing element error handling and self-clearing with missing or extraneous control code feature Marc A. Quattromani, Jeffery L. Moll 2002-06-18
6026444 TORUS routing element error handling and self-clearing with link lockup prevention Marc A. Quattromani, Jeffery L. Moll 2000-02-15
6016510 TORUS routing element error handling and self-clearing with programmable watermarking Marc A. Quattromani 2000-01-18
5787095 Multiprocessor computer backlane bus Stacey G. Lloyd, Richard Stout, Robert Takasumi, John Lynch 1998-07-28
5784456 Single-line multi-handset telephone Kevin Carey 1998-07-21
5581713 Multiprocessor computer backplane bus in which bus transactions are classified into different classes for arbitration Stacey G. Lloyd, Richard Stout, Robert Takasumi, John Lynch 1996-12-03
5050066 Apparatus with a single memory and a plurality of queue counters for queuing requests and replies on a pipelined packet bus Eileen Riggs 1991-09-17
5006982 Method of increasing the bandwidth of a packet bus by reordering reply packets Ronald J. Ebersole, David B. Johnson, David L. Budde, Gerhard Bier 1991-04-09
4903270 Apparatus for self checking of functional redundancy check (FRC) logic David B. Johnson, Eileen Riggs 1990-02-20
4821271 Methods and circuits for checking integrated circuit chips having programmable outputs M. Vittal Kini, Sunil Shenoy 1989-04-11
4792955 Apparatus for on-line checking and reconfiguration of integrated circuit chips David B. Johnson, Stanley P. Kenoyer, Sven-Axel Nilsson 1988-12-20
4785428 Programmable memory array control signals Atiq Bajwa, Robert C. Duzett, M. Vittal Kini, Kent Mason, Sunil Shenoy 1988-11-15