Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5944817 | Method and apparatus for implementing a set-associative branch target buffer | Bradley D. Hoyt, Glenn Hinton, David B. Papworth, Ashwani K. Gupta, Michael A. Fetterman +2 more | 1999-08-31 |
| 5903751 | Method and apparatus for implementing a branch target buffer in CISC processor | Bradley D. Hoyt, Glenn J. Hinton, David B. Papworth, Ashwani K. Gupta, Michael A. Fetterman +2 more | 1999-05-11 |
| 5870599 | Computer system employing streaming buffer for instruction preetching | Glenn J. Hinton, Ashwani K. Gupta | 1999-02-09 |
| 5812839 | Dual prediction branch system having two step of branch recovery process which activated only when mispredicted branch is the oldest instruction in the out-of-order unit | Bradley D. Hoyt, Glenn J. Hinton, David B. Papworth, Ashwani K. Gupta, Michael A. Fetterman +2 more | 1998-09-22 |
| 5768576 | Method and apparatus for predicting and handling resolving return from subroutine instructions in a computer processor | Bradley D. Hoyt, Glenn J. Hinton, David B. Papworth, Ashwani K. Gupta, Michael A. Fetterman +2 more | 1998-06-16 |
| 5749092 | Method and apparatus for using a direct memory access unit and a data cache unit in a microprocessor | Jay Heeb, Jimmy Wong | 1998-05-05 |
| 5706492 | Method and apparatus for implementing a set-associative branch target buffer | Bradley D. Hoyt, Glenn Hinton, David B. Papworth, Ashwani K. Gupta, Michael A. Fetterman +2 more | 1998-01-06 |
| 5604877 | Method and apparatus for resolving return from subroutine instructions in a computer processor | Bradley D. Hoyt, Glenn J. Hinton, David B. Papworth, Ashwani K. Gupta, Michael A. Fetterman +2 more | 1997-02-18 |
| 5590368 | Method and apparatus for dynamically expanding the pipeline of a microprocessor | Jay Heeb, Jimmy Wong | 1996-12-31 |
| 5574871 | Method and apparatus for implementing a set-associative branch target buffer | Bradley D. Hoyt, Glenn J. Hinton, David B. Papworth, Ashwani K. Gupta, Michael A. Fetterman +2 more | 1996-11-12 |
| 5574923 | Method and apparatus for performing bi-endian byte and short accesses in a single-endian microprocessor | Jay Heeb, Scott Huck | 1996-11-12 |
| 5493667 | Apparatus and method for an instruction cache locking scheme | Scott Huck, Konrad K. Lai, Larry Smith | 1996-02-20 |
| 5455924 | Apparatus and method for partial execution blocking of instructions following a data cache miss | James Wah Hou Wong | 1995-10-03 |
| 5313605 | High bandwith output hierarchical memory store including a cache, fetch buffer and ROM | Scott Huck, Frank S. Smith | 1994-05-17 |
| 4821271 | Methods and circuits for checking integrated circuit chips having programmable outputs | M. Vittal Kini, Mark S. Myers | 1989-04-11 |
| 4785428 | Programmable memory array control signals | Atiq Bajwa, Robert C. Duzett, M. Vittal Kini, Kent Mason, Mark S. Myers | 1988-11-15 |