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Sunil Shenoy — 16 Patents

Intel: 16 patents #2,596 of 30,777Top 9%
Beaverton, OR: #376 of 3,140 inventorsTop 15%
Oregon: #2,717 of 28,073 inventorsTop 10%
Overall (All Time): #284,196 of 4,157,543Top 7%
16 Patents All Time
Sunil Shenoy has been granted 16 US patents while listed as an inventor at Intel. The first was granted in 1988 and the most recent in August 1999. Sunil Shenoy ranks #284,196 of 4,157,543 US inventors in our database (top 6.8%). Patent records list Sunil Shenoy in Beaverton, OR, US.

Issued Patents All Time

Showing 1–16 of 16 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
5944817 Method and apparatus for implementing a set-associative branch target buffer Bradley D. Hoyt, Glenn Hinton, David B. Papworth, Ashwani K. Gupta, Michael A. Fetterman +2 more 1999-08-31 $176,323,000
5903751 Method and apparatus for implementing a branch target buffer in CISC processor Bradley D. Hoyt, Glenn J. Hinton, David B. Papworth, Ashwani K. Gupta, Michael A. Fetterman +2 more 1999-05-11 $87,534,000
5870599 Computer system employing streaming buffer for instruction preetching Glenn J. Hinton, Ashwani K. Gupta 1999-02-09 $168,808,000
5812839 Dual prediction branch system having two step of branch recovery process which activated only when mispredicted branch is the oldest instruction in the out-of-order unit Bradley D. Hoyt, Glenn J. Hinton, David B. Papworth, Ashwani K. Gupta, Michael A. Fetterman +2 more 1998-09-22 $64,376,000
5768576 Method and apparatus for predicting and handling resolving return from subroutine instructions in a computer processor Bradley D. Hoyt, Glenn J. Hinton, David B. Papworth, Ashwani K. Gupta, Michael A. Fetterman +2 more 1998-06-16 $42,844,000
5749092 Method and apparatus for using a direct memory access unit and a data cache unit in a microprocessor Jay Heeb, Jimmy Wong 1998-05-05 $55,348,000
5706492 Method and apparatus for implementing a set-associative branch target buffer Bradley D. Hoyt, Glenn Hinton, David B. Papworth, Ashwani K. Gupta, Michael A. Fetterman +2 more 1998-01-06 $96,219,000
5604877 Method and apparatus for resolving return from subroutine instructions in a computer processor Bradley D. Hoyt, Glenn J. Hinton, David B. Papworth, Ashwani K. Gupta, Michael A. Fetterman +2 more 1997-02-18 $59,389,000
5590368 Method and apparatus for dynamically expanding the pipeline of a microprocessor Jay Heeb, Jimmy Wong 1996-12-31 $60,124,000
5574871 Method and apparatus for implementing a set-associative branch target buffer Bradley D. Hoyt, Glenn J. Hinton, David B. Papworth, Ashwani K. Gupta, Michael A. Fetterman +2 more 1996-11-12 $38,860,000
5574923 Method and apparatus for performing bi-endian byte and short accesses in a single-endian microprocessor Jay Heeb, Scott Huck 1996-11-12 $38,860,000
5493667 Apparatus and method for an instruction cache locking scheme Scott Huck, Konrad K. Lai, Larry Smith 1996-02-20 $70,627,000
5455924 Apparatus and method for partial execution blocking of instructions following a data cache miss James Wah Hou Wong 1995-10-03 $55,152,000
5313605 High bandwith output hierarchical memory store including a cache, fetch buffer and ROM Scott Huck, Frank S. Smith 1994-05-17 $92,612,000
4821271 Methods and circuits for checking integrated circuit chips having programmable outputs M. Vittal Kini, Mark S. Myers 1989-04-11 $23,566,000
4785428 Programmable memory array control signals Atiq Bajwa, Robert C. Duzett, M. Vittal Kini, Kent Mason, Mark S. Myers 1988-11-15 $9,472,000