Issued Patents All Time
Showing 25 most recent of 60 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12130740 | Apparatuses and methods for a processor architecture | Jason W. Brandt, Robert S. Chappell, Jesus Corbal, Edward T. Grochowski, Stephen H. Gunther +9 more | 2024-10-29 |
| 11294809 | Apparatuses and methods for a processor architecture | Jason W. Brandt, Robert S. Chappell, Jesus Corbal, Edward T. Grochowski, Stephen H. Gunther +9 more | 2022-04-05 |
| 10469557 | QoS based binary translation and application streaming | Bharath Muthiah, William Rash, Glenn J. Hinton, Martin G. Dixon, Scott D. Hahn | 2019-11-05 |
| 10282296 | Zeroing a cache line | Jason W. Brandt, Robert S. Chappell, Jesus Corbal, Edward T. Grochowski, Stephen H. Gunther +5 more | 2019-05-07 |
| 9525586 | QoS based binary translation and application streaming | Bharath Muthiah, William Rash, Glenn J. Hinton, Martin G. Dixon, Scott Hayn | 2016-12-20 |
| 6393550 | Method and apparatus for pipeline streamlining where resources are immediate or certainly retired | Michael A. Fetterman, Glenn J. Hinton, Robert W. Martell | 2002-05-21 |
| 6349380 | Linear address extension and mapping to physical memory using 4 and 8 byte page table entries in a 32-bit microprocessor | Shahrokh Shahidzadeh, Bryant Bigbee, Frank Binns, Robert P. Colwell | 2002-02-19 |
| 6101597 | Method and apparatus for maximum throughput scheduling of dependent operations in a pipelined processor | Robert P. Colwell, Michael A. Fetterman, Glenn J. Hinton, Robert W. Martell | 2000-08-08 |
| 6079014 | Processor that redirects an instruction fetch pipeline immediately upon detection of a mispredicted branch while committing prior instructions to an architectural state | Michael A. Fetterman, Andrew F. Glew, Robert P. Colwell, Glenn J. Hinton | 2000-06-20 |
| 5987600 | Exception handling in a processor that performs speculative out-of-order instruction execution | Glenn J. Hinton, Michael A. Fetterman, Robert P. Colwell, Andrew F. Glew | 1999-11-16 |
| 5974523 | Mechanism for efficiently overlapping multiple operand types in a microprocessor | Andrew F. Glew, Darrell D. Boggs, Michael A. Fetterman, Glenn J. Hinton, Robert P. Colwell | 1999-10-26 |
| 5944817 | Method and apparatus for implementing a set-associative branch target buffer | Bradley D. Hoyt, Glenn Hinton, Ashwani K. Gupta, Michael A. Fetterman, Subramanian Natarajan +2 more | 1999-08-31 |
| 5918046 | Method and apparatus for a branch instruction pointer table | Bradley D. Hoyt, Glenn J. Hinton, Subramanian Natarajan, Reynold V. D'Sa | 1999-06-29 |
| 5913050 | Method and apparatus for providing address-size backward compatibility in a processor using segmented memory | Darrell D. Boggs, Robert P. Colwell, Michael A. Fetterman, Andrew F. Glew, Glenn J. Hinton | 1999-06-15 |
| 5903751 | Method and apparatus for implementing a branch target buffer in CISC processor | Bradley D. Hoyt, Glenn J. Hinton, Ashwani K. Gupta, Michael A. Fetterman, Subramanian Natarajan +2 more | 1999-05-11 |
| 5842036 | Circuit and method for scheduling instructions by predicting future availability of resources required for execution | Glenn J. Hinton, Robert W. Martell, Michael A. Fetterman, James L. Schwartz | 1998-11-24 |
| 5826094 | Register alias table update to indicate architecturally visible state | Robert P. Colwell, Michael A. Fetterman, Andrew F. Glew, Glenn J. Hinton | 1998-10-20 |
| 5826109 | Method and apparatus for performing multiple load operations to the same memory location in a computer system | Jeffery M. Abramson, Haitham Akkary, Andrew F. Glew, Glenn J. Hinton, Kris G. Konigsfeld +2 more | 1998-10-20 |
| 5812839 | Dual prediction branch system having two step of branch recovery process which activated only when mispredicted branch is the oldest instruction in the out-of-order unit | Bradley D. Hoyt, Glenn J. Hinton, Ashwani K. Gupta, Michael A. Fetterman, Subramanian Natarajan +2 more | 1998-09-22 |
| 5809325 | Circuit and method for scheduling instructions by predicting future availability of resources required for execution | Glenn J. Hinton, Robert W. Martell, Michael A. Fetterman, James L. Schwartz | 1998-09-15 |
| 5809271 | Method and apparatus for changing flow of control in a processor | Robert P. Colwell, Atiq Bajwa, Michael A. Fetterman, Andrew F. Glew, Glenn J. Hinton | 1998-09-15 |
| 5778407 | Methods and apparatus for determining operating characteristics of a memory element based on its physical location | Andrew F. Glew, Glenn J. Hinton, Michael A. Fetterman, Robert P. Colwell, Frederick J. Pollack | 1998-07-07 |
| 5778245 | Method and apparatus for dynamic allocation of multiple buffers in a processor | Andrew F. Glew, Glenn J. Hinton, Robert P. Colwell, Michael A. Fetterman, Shantanu Gupta +1 more | 1998-07-07 |
| 5768576 | Method and apparatus for predicting and handling resolving return from subroutine instructions in a computer processor | Bradley D. Hoyt, Glenn J. Hinton, Ashwani K. Gupta, Michael A. Fetterman, Subramanian Natarajan +2 more | 1998-06-16 |
| 5751986 | Computer system with self-consistent ordering mechanism | Michael A. Fetterman, Glenn J. Hinton, Andrew F. Glew, Robert P. Colwell | 1998-05-12 |