Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and apparatus for providing address-size backward compatibility in a processor using segmented memory

Method and apparatus for providing address-size backward compatibility in a processor using segmented memory

US Patent 5913050 · Granted Jun 15, 1999

Estimated economic value: $278,496,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Systems and methods for multicasting data2025
Cache memory with per-sector cache residency controls2025
Apparatuses and methods for a processor architecture2024
Hybrid allocation of data lines in a streaming cache memory2024
Techniques for interleaving textures2023
Out of order memory request tracking structure and technique2023
Device, method and system for providing a stacked arrangement of integrated circ2023
Techniques for performing accelerated point sampling in a texture processing pip2022
Device, method and system for providing a stacked arrangement of integrated circ2022
Apparatuses and methods for a processor architecture2022
Dynamic partial power down of memory-side cache in a 2-level memory hierarchy2021
Apparatus and method for implementing a multi-level memory hierarchy having diff2021