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Robert P. Colwell — 40 Patents

Intel: 35 patents #1,029 of 30,777Top 4%
DEDigital Equipment: 3 patents #412 of 2,100Top 20%
Guilford, CT: #24 of 437 inventorsTop 6%
Connecticut: #704 of 34,797 inventorsTop 3%
Overall (All Time): #78,057 of 4,157,543Top 2%
40 Patents All Time
Robert P. Colwell has been granted 40 US patents while listed as an inventor at Intel. The first was granted in 1989 and the most recent in February 2002. Robert P. Colwell ranks #78,057 of 4,157,543 US inventors in our database (top 1.9%). Patent records list Robert P. Colwell in Guilford, CT, US.

Issued Patents All Time

Showing 1–25 of 40 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
6349380 Linear address extension and mapping to physical memory using 4 and 8 byte page table entries in a 32-bit microprocessor Shahrokh Shahidzadeh, Bryant Bigbee, David B. Papworth, Frank Binns 2002-02-19 $213,043,000
6101597 Method and apparatus for maximum throughput scheduling of dependent operations in a pipelined processor Michael A. Fetterman, Glenn J. Hinton, Robert W. Martell, David B. Papworth 2000-08-08 $246,908,000
6079014 Processor that redirects an instruction fetch pipeline immediately upon detection of a mispredicted branch while committing prior instructions to an architectural state David B. Papworth, Michael A. Fetterman, Andrew F. Glew, Glenn J. Hinton 2000-06-20 $289,858,000
6079033 Self-monitoring distributed hardware systems James E. Jacobson, Jr. 2000-06-20 $289,858,000
6047369 Flag renaming and flag masks within register alias table Andrew F. Glew, Atiq Bajwa, Glenn J. Hinton, Michael A. Fetterman 2000-04-04 $215,158,000
5987600 Exception handling in a processor that performs speculative out-of-order instruction execution David B. Papworth, Glenn J. Hinton, Michael A. Fetterman, Andrew F. Glew 1999-11-16 $116,169,000
5974523 Mechanism for efficiently overlapping multiple operand types in a microprocessor Andrew F. Glew, Darrell D. Boggs, Michael A. Fetterman, Glenn J. Hinton, David B. Papworth 1999-10-26 $114,137,000
5913050 Method and apparatus for providing address-size backward compatibility in a processor using segmented memory Darrell D. Boggs, Michael A. Fetterman, Andrew F. Glew, Glenn J. Hinton, David B. Papworth 1999-06-15 $278,496,000
5826094 Register alias table update to indicate architecturally visible state David B. Papworth, Michael A. Fetterman, Andrew F. Glew, Glenn J. Hinton 1998-10-20 $74,450,000
5809271 Method and apparatus for changing flow of control in a processor Atiq Bajwa, Michael A. Fetterman, Andrew F. Glew, Glenn J. Hinton, David B. Papworth 1998-09-15 $52,435,000
5778245 Method and apparatus for dynamic allocation of multiple buffers in a processor David B. Papworth, Andrew F. Glew, Glenn J. Hinton, Michael A. Fetterman, Shantanu Gupta +1 more 1998-07-07 $55,069,000
5778407 Methods and apparatus for determining operating characteristics of a memory element based on its physical location Andrew F. Glew, Glenn J. Hinton, David B. Papworth, Michael A. Fetterman, Frederick J. Pollack 1998-07-07 $55,069,000
5751986 Computer system with self-consistent ordering mechanism Michael A. Fetterman, Glenn J. Hinton, David B. Papworth, Andrew F. Glew 1998-05-12 $59,372,000
5729728 Method and apparatus for predicting, clearing and redirecting unpredicted changes in instruction flow in a microprocessor Atiq Bajwa, Michael A. Fetterman, Andrew F. Glew, Glenn J. Hinton, David B. Papworth 1998-03-17 $93,098,000
5727176 Data processor with circuitry for handling pointers associated with a register exchange operation David W. Clift, James M. Arnold, Andrew F. Glew 1998-03-10 $101,484,000
5721855 Method for pipeline processing of instructions by controlling access to a reorder buffer using a register file outside the reorder buffer Glenn J. Hinton, David B. Papworth, Andrew F. Glew, Michael A. Fetterman 1998-02-24 $81,053,000
5687338 Method and apparatus for maintaining a macro instruction for refetching in a pipelined processor Darrell D. Boggs, Michael A. Fetterman, Andrew F. Glew, Ashwani K. Gupta, Glenn J. Hinton +1 more 1997-11-11 $176,544,000
5627985 Speculative and committed resource files in an out-of-order processor Michael A. Fetterman, Andrew F. Glew, David B. Papworth, Glenn J. Hinton 1997-05-06 $112,956,000
5615385 Method and apparatus for zero extension and bit shifting to preserve register parameters in a microprocessor utilizing register renaming Michael A. Fetterman, Andrew F. Glew, Glenn J. Hinton, David B. Papworth 1997-03-25 $124,284,000
5613132 Integer and floating point register alias table within processor device David W. Clift, James M. Arnold, Andrew F. Glew 1997-03-18 $60,088,000
5604878 Method and apparatus for avoiding writeback conflicts between execution units sharing a common writeback path Michael A. Fetterman, Andrew F. Glew, Glenn J. Hinton, Robert W. Martell, David B. Papworth 1997-02-18 $59,389,000
5584038 Entry allocation in a circular buffer using wrap bits indicating whether a queue of the circular buffer has been traversed David B. Papworth, Andrew F. Glew, Michael A. Fetterman, Glenn J. Hinton, Steven J. Griffith +2 more 1996-12-10 $92,105,000
5584037 Entry allocation in a circular buffer David B. Papworth, Andrew F. Glew, Michael A. Fetterman, Glenn J. Hinton, Steven J. Griffith +2 more 1996-12-10 $92,105,000
5574942 Hybrid execution unit for complex microprocessor David B. Papworth, Michael A. Fetterman, Andrew F. Glew, Glenn J. Hinton, Stephen M. Coward +1 more 1996-11-12 $38,860,000
5564111 Method and apparatus for implementing a non-blocking translation lookaside buffer Andrew F. Glew, Haitham Akkary, Glenn J. Hinton, David B. Papworth, Michael A. Fetterman 1996-10-08 $89,581,000