Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Device, method and system for providing a stacked arrangement of integrated circuit dies

Device, method and system for providing a stacked arrangement of integrated circuit dies

US Patent 11373987 · Granted Jun 28, 2022

Estimated economic value: $15,065,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Integrated circuit interconnect structures with a metal chalcogenide liner2025
Package architecture of photonic system with vertically stacked dies having plan2025
Package architecture of scalable compute wall having compute bricks with vertica2025
Performing distributed processing using distributed memory2025
Embedded dynamic random-access memory (eDRAM) to operate based on data access ch2025
Integrated planar transistors and memory cell array architectures2025
Three-dimensional nanoribbon-based hysteretic memory2025
Integrated circuit devices with angled transistors formed based on angled wafers2025
Integrated circuit structures having ultra-high conductivity global routing2025
Transistor with front-side and back-side contacts and routing2025
Providing fine grain access to package memory2025
Cooling approaches for stitched dies2025