SN

Subramanian Natarajan

IN Intel: 10 patents #4,046 of 30,777Top 15%
NE Netapp: 7 patents #289 of 1,846Top 20%
Overall (All Time): #265,264 of 4,157,543Top 7%
17
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12339752 Techniques for LIF placement in san storage cluster synchronous disaster recovery Raj Lalsangi, Pramod John Mathew, Santosh Rao 2025-06-24
11940954 Methods for ensuring correctness of file system analytics and devices thereof Richard P. Jernigan, IV, Xin Wang, Richard Chow, Adam F. Ciapponi, Brad Lisson +1 more 2024-03-26
11782805 Techniques for LIF placement in SAN storage cluster synchronous disaster recovery Raj Lalsangi, Pramod John Mathew, Santosh Rao 2023-10-10
11561935 Methods for ensuring correctness of file system analytics and devices thereof Richard P. Jernigan, IV, Xin Wang, Richard Chow, Adam F. Ciapponi, Brad Lisson +1 more 2023-01-24
11487632 Techniques for LIF placement in SAN storage cluster synchronous disaster recovery Raj Lalsangi, Pramod John Mathew, Santosh Ananth Rao 2022-11-01
10769037 Techniques for LIF placement in san storage cluster synchronous disaster recovery Raj Lalsangi, Pramod John Mathew, Santosh Ananth Rao 2020-09-08
9965363 Techniques for LIF placement in SAN storage cluster synchronous disaster recovery Raj Lalsangi, Pramod John Mathew, Santosh Ananth Rao 2018-05-08
5944817 Method and apparatus for implementing a set-associative branch target buffer Bradley D. Hoyt, Glenn Hinton, David B. Papworth, Ashwani K. Gupta, Michael A. Fetterman +2 more 1999-08-31
5918046 Method and apparatus for a branch instruction pointer table Bradley D. Hoyt, Glenn J. Hinton, David B. Papworth, Reynold V. D'Sa 1999-06-29
5903751 Method and apparatus for implementing a branch target buffer in CISC processor Bradley D. Hoyt, Glenn J. Hinton, David B. Papworth, Ashwani K. Gupta, Michael A. Fetterman +2 more 1999-05-11
5812839 Dual prediction branch system having two step of branch recovery process which activated only when mispredicted branch is the oldest instruction in the out-of-order unit Bradley D. Hoyt, Glenn J. Hinton, David B. Papworth, Ashwani K. Gupta, Michael A. Fetterman +2 more 1998-09-22
5768576 Method and apparatus for predicting and handling resolving return from subroutine instructions in a computer processor Bradley D. Hoyt, Glenn J. Hinton, David B. Papworth, Ashwani K. Gupta, Michael A. Fetterman +2 more 1998-06-16
5706492 Method and apparatus for implementing a set-associative branch target buffer Bradley D. Hoyt, Glenn Hinton, David B. Papworth, Ashwani K. Gupta, Michael A. Fetterman +2 more 1998-01-06
5604877 Method and apparatus for resolving return from subroutine instructions in a computer processor Bradley D. Hoyt, Glenn J. Hinton, David B. Papworth, Ashwani K. Gupta, Michael A. Fetterman +2 more 1997-02-18
5584001 Branch target buffer for dynamically predicting branch instruction outcomes using a predicted branch history Bradley D. Hoyt, Glenn J. Hinton, Andrew F. Glew 1996-12-10
5577217 Method and apparatus for a branch target buffer with shared branch pattern tables for associated branch predictions Bradley D. Hoyt 1996-11-19
5574871 Method and apparatus for implementing a set-associative branch target buffer Bradley D. Hoyt, Glenn J. Hinton, David B. Papworth, Ashwani K. Gupta, Michael A. Fetterman +2 more 1996-11-12