RD

Reynold V. D'Sa

IN Intel: 15 patents #2,741 of 30,777Top 9%
Overall (All Time): #326,447 of 4,157,543Top 8%
15
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
7334115 Detection, recovery and prevention of bogus branches Alan B. Kyker, Slade Morgan, Rebecca E. Hebda, Richard A. Weier, Robert F. Krick 2008-02-19
6715064 Method and apparatus for performing sequential executions of elements in cooperation with a transform Slade Morgan, Alan B. Kyker, Gad Sheaffer, Gustavo P. Espinosa 2004-03-30
6493821 Recovery from writeback stage event signal or micro-branch misprediction using instruction sequence number indexed state information table Robert F. Krick, Rebecca E. Hebda, Alan B. Kyker 2002-12-10
6374350 System and method of maintaining and utilizing multiple return stack buffers Rebecca E. Hebda, Stavros Kalafatis, Alan B. Kyker, Robert B. Chaput 2002-04-16
6151671 System and method of maintaining and utilizing multiple return stack buffers Rebecca E. Hebda, Stavros Kalafatis, Alan B. Kyker, Robert B. Chaput 2000-11-21
6055630 System and method for processing a plurality of branch instructions by a plurality of storage devices and pipeline units Alan B. Kyker, Gad Sheaffer, Gustavo P. Espinosa, Stavros Kalafatis, Rebecca E. Hebda 2000-04-25
6014742 Trace branch prediction unit Robert F. Krick, Chan Woo Lee 2000-01-11
5944817 Method and apparatus for implementing a set-associative branch target buffer Bradley D. Hoyt, Glenn Hinton, David B. Papworth, Ashwani K. Gupta, Michael A. Fetterman +2 more 1999-08-31
5918046 Method and apparatus for a branch instruction pointer table Bradley D. Hoyt, Glenn J. Hinton, David B. Papworth, Subramanian Natarajan 1999-06-29
5903751 Method and apparatus for implementing a branch target buffer in CISC processor Bradley D. Hoyt, Glenn J. Hinton, David B. Papworth, Ashwani K. Gupta, Michael A. Fetterman +2 more 1999-05-11
5812839 Dual prediction branch system having two step of branch recovery process which activated only when mispredicted branch is the oldest instruction in the out-of-order unit Bradley D. Hoyt, Glenn J. Hinton, David B. Papworth, Ashwani K. Gupta, Michael A. Fetterman +2 more 1998-09-22
5768576 Method and apparatus for predicting and handling resolving return from subroutine instructions in a computer processor Bradley D. Hoyt, Glenn J. Hinton, David B. Papworth, Ashwani K. Gupta, Michael A. Fetterman +2 more 1998-06-16
5706492 Method and apparatus for implementing a set-associative branch target buffer Bradley D. Hoyt, Glenn Hinton, David B. Papworth, Ashwani K. Gupta, Michael A. Fetterman +2 more 1998-01-06
5604877 Method and apparatus for resolving return from subroutine instructions in a computer processor Bradley D. Hoyt, Glenn J. Hinton, David B. Papworth, Ashwani K. Gupta, Michael A. Fetterman +2 more 1997-02-18
5574871 Method and apparatus for implementing a set-associative branch target buffer Bradley D. Hoyt, Glenn J. Hinton, David B. Papworth, Ashwani K. Gupta, Michael A. Fetterman +2 more 1996-11-12